On the SiO[sub2]-Based Gate-Dielectric Scaling Limit for Low-Standby Power Applications in the Context of a 0.13 μ m CMOS Logic Technology.

Autor: Yo-Sheng Lin, Huan-Tsung Huang, Chung-Cheng Wu, Ying-Keung Leung, Hsu-Yang Pan, Tse-En Chang, Wei-Ming Chen, Jung-Jih Liaw, Diaz, Carlos H.

Publikováno v: IEEE Transactions on Electron Devices; Mar2002, Vol. 49 Issue 3, p442, 7p, 1 Black and White Photograph, 1 Chart, 12 Graphs