Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Jung-Hoe Choi"'
Autor:
Jürgen Preuninger, Ulrich Klostermann, Jongsu Kim, Hans-Jürgen Stock, Ulrich Welling, Sang-Yil Chang, Hyungju Ryu, Kyoung-sub Shin, Wolfgang Demmerle, Eunsoo Jeong, Hyekyoung Jue, Joon-Soo Park, Jung-Hoe Choi, Sang-Jin Kim
Publikováno v:
Extreme Ultraviolet (EUV) Lithography XI.
For the past years, ArF immersion has been employed as the major lithography tool in the foundry manufacturing to fabricate the patterns of minimum pitch and size. However, for semiconductor scaling beyond N7 the application of EUV lithography is con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab0c4bfe75ff6b348a87b2afdefcea26
https://doi.org/10.1117/12.2553319
https://doi.org/10.1117/12.2553319
Autor:
Jaeseung Choi, Guangming Xiao, Jung-Hoe Choi, Thuc Dam, Jinhyuck Jun, Hyunjo Yang, Chanha Park, Munhoe Do, Se-Young Oh, Dong Chan Lee, Jaehee Hwang, Kevin Lucas
Publikováno v:
SPIE Proceedings.
Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88d427dff04fbe213c681ea1c8a4cbb9
https://doi.org/10.1117/12.2257857
https://doi.org/10.1117/12.2257857
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3082-3085
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7be999a8956b3a8af7b83348dd9f0c1f
https://doi.org/10.1587/transfun.e92.a.3082
https://doi.org/10.1587/transfun.e92.a.3082
Autor:
Donggyu Yim, Minwoo Park, Hyunjo Yang, Jung-Hoe Choi, Gerard Luk-Pat, Alex Miloslavsky, Taehoon Kim, Jinhyuck Jun, Dong Chan Lee, Chanha Park, Munhoe Do
Publikováno v:
SPIE Proceedings.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits, sub-resolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufactur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d4b2a5b8a5f194ff88ee34602245239
https://doi.org/10.1117/12.2085460
https://doi.org/10.1117/12.2085460
Autor:
Chanha Park, Thomas Schmoeller, Bernd Kuechler, Donggyu Yim, Munhoe Do, Hyunjo Yang, Rainer Zimmermann, Thomas Muelders, Ulrich Klostermann, Shinyoung Kim, Jung-Hoe Choi, Jinhyuck Jeon
Publikováno v:
SPIE Proceedings.
DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern proce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f89d5529b9aaac9d62c1cd0a5fa4e61d
https://doi.org/10.1117/12.2046541
https://doi.org/10.1117/12.2046541
Autor:
Chan Ha Park, Tom Cecil, Dave Kim, Sung-Woo Lee, Jinhyuck Jeon, Mindy Lee, Seung-Hee Baek, Kevin Lucas, Jung-Hoe Choi, Guangming Xiao
Publikováno v:
SPIE Proceedings.
Model-driven target optimization using an ILT hotspot fixer is applied to line collapsing defects of 2- dimensional randomtest pattern of a very low K1 process. The target is moved by minimizing the process variation band and the pitches of hotspot p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7d6193b8820f09e004ebb016915fd54
https://doi.org/10.1117/12.2026140
https://doi.org/10.1117/12.2026140
Autor:
Anthony Chunqing Wang, Jungchan Kim, Taehyeong Lee, Chanha Park, Sung-Woo Lee, Donggyu Yim, Irene Su, Jeonkyu Lee, Hyunjo Yang, Robert E Boone, Jaeseung Choi, Munhoe Do, Yongfa Fan, Kevin Lucas, Jung-Hoe Choi, Hua Song, Sangjin Oh, Chunsoo Kang
Publikováno v:
SPIE Proceedings.
Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very success
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::691bb9e7be340ea02a0ae6b36e8388a9
https://doi.org/10.1117/12.2012463
https://doi.org/10.1117/12.2012463
Autor:
Jinhyuck Jeon, Donggyu Yim, Munhoe Do, Shinyoung Kim, Yunqiang Zhang, Kevin Hooker, Jung-Hoe Choi, Stephen Jang, Chanha Park, Hyunjo Yang, Brian Ward, Jookyoung Song
Publikováno v:
SPIE Proceedings.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacture
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca36ab713d38ea304ae2904ff29bbc01
https://doi.org/10.1117/12.2011450
https://doi.org/10.1117/12.2011450
Publikováno v:
SPIE Proceedings.
As IC design complexity keeps increasing, it is more and more difficult to ensure the pattern transfer after optical proximity correction (OPC) due to the continuous reduction of layout dimensions and lithographic limitation by k1 factor. To guarante
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27fd11395d3b0a1dcfbe1de78b1fb34b
https://doi.org/10.1117/12.870707
https://doi.org/10.1117/12.870707
Autor:
Dong-Hyun Kim, Jung-Hoe Choi, Sanghoon Lee, Jun-Dong Cho, Chul-Hong Park, Yong-Hee Park, Ji-Suk Hong, Moon-Hyun Yoo
Publikováno v:
SPIE Proceedings.
While predicting and removing of lithographic hot-spots are a matured practice in recent semiconductor industry, it is one of the most difficult challenges to achieve high quality detection coverage and to provide designer-friendly fixing guidance fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::190cf7d8881c8dac7b6cad565f153f6c
https://doi.org/10.1117/12.811840
https://doi.org/10.1117/12.811840