Zobrazeno 1 - 9 of 9 pro vyhledávání: '"Jung Yoon Hwang"'
4
Modeling of Integrated Circuit Yield Using a Spatial Nonhomogeneous Poisson Process
Autor: Way Kuo, Jung Yoon Hwang, Chunghun Ha
Publikováno v: IEEE Transactions on Semiconductor Manufacturing. 24:377-384
This paper proposes a new yield model for integrated circuits using a spatial point process. The defect density variation by location on a wafer is modeled by a spatial nonhomogeneous Poisson process. The intensity function of the yield model describ
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::dcd8d4dc00d3565f74258f43788571b7
https://doi.org/10.1109/tsm.2011.2143733
Zobrazit plný text záznamu
5
Accurate Conjunction of Yield Models for Fault-Tolerant Memory Integrated Circuits
Autor: Jung Yoon Hwang, Chunghun Ha, Way Kuo
Publikováno v: IEEE Transactions on Semiconductor Manufacturing. 22:344-350
Critical defects, i.e., faults, inevitably occur during semiconductor fabrication, and they significantly reduce both manufacturing yield and product reliability. To decrease the effects of the defects, several fault-tolerance methods, such as the re
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4a439d4fed3629c6d4ac3dd99e65759e
https://doi.org/10.1109/tsm.2009.2024843
Zobrazit plný text záznamu
6
Yield prediction via spatial modeling of clustered defect counts across a wafer map
Autor: Jung Yoon Hwang, Way Kuo, Suk Joo Bae
Publikováno v: IIE Transactions. 39:1073-1083
In this paper we propose spatial modeling approaches for clustered defects observed using an Integrated Circuit (IC) wafer map. We use the spatial location of each IC chip on the wafer as a covariate for the corresponding defect count listed in the w
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::dbfb65eea5f6ea55da138c8822b4f5d1
https://doi.org/10.1080/07408170701275335
Zobrazit plný text záznamu
7
Model-based clustering for integrated circuit yield enhancement
Autor: Way Kuo, Jung Yoon Hwang
Publikováno v: European Journal of Operational Research. 178:143-153
This paper studies the defect data analysis method for semiconductor yield enhancement. Given the defect locations on a wafer, the local defects generated from the assignable causes are classified from the global defects generated from the random cau
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1cff35bd8578f6865afe657c9a6ae1f8
https://doi.org/10.1016/j.ejor.2005.11.032
Zobrazit plný text záznamu
8
Akademický článek
Parametric Yield Modeling Using Hidden Variable Logistic Regression.
Autor: JUNG YOON HWANG1 jungyoon.hwang@samsung.com, HYUN CHEOL LEE2 hclee@kau.ac.kr
Publikováno v: Journal of Quality Technology. Oct2014, Vol. 46 Issue 4, p323-339. 17p.
Zobrazit plný text záznamu
9
Akademický článek
Accurate Conjunction of Yield Models for Fault-Tolerant Memory Integrated Circuits.
Autor: Chunghun Ha, Way Kuo, Jung Yoon Hwang
Publikováno v: IEEE Transactions on Semiconductor Manufacturing; Aug2009, Vol. 22 Issue 3, p344-350, 7p, 3 Black and White Photographs, 4 Graphs
Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání

Omezení vyhledávání
Plný text Recenzováno Digitální knihovna AV ČR
Zdroje