Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Jung‐Pil Lim"'
Autor:
Yong‐Yun Park, Won‐Ho Jang, Kyong‐Ho Kim, Kyungho Ryu, Jung‐Pil Lim, Yongil Kwon, Hyun‐Wook Lim, Jae‐Youl Lee
Publikováno v:
Journal of the Society for Information Display. 31:241-252
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c465c5e07f27ce24d215c6b20c66d56
https://doi.org/10.1002/jsid.1225
https://doi.org/10.1002/jsid.1225
Autor:
Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02180683fe14cc816c2ad62edfa5a2f0
https://doi.org/10.1109/isscc42615.2023.10067592
https://doi.org/10.1109/isscc42615.2023.10067592
Autor:
Jin-Ho Kim, Jae-Youl Lee, Kyungho Ryu, Hyun-Wook Lim, Jung-Pil Lim, Kil-Hoon Lee, Junho Park, Hansu Pae
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:2257-2267
This article presents the theoretical analyses and experimental results about jitter tolerance for delay-locked loop (DLL)-based clock and data recovery (CDR), which is generally used in an embedded clock serial link. From the proposed S-domain model
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f67838e6563aa91b3a209a9598320df
https://doi.org/10.1109/tvlsi.2020.3018794
https://doi.org/10.1109/tvlsi.2020.3018794
Autor:
Wonho Tak, Gyoo-Cheol Hwang, Hansu Pae, Kil-Hoon Lee, Jae-Youl Lee, Dong-Myung Lee, Yoon Kyung Choi, Jung-Pil Lim
Publikováno v:
SID Symposium Digest of Technical Papers. 45:286-288
An enhanced reduced voltage differential signaling (eRVDS) intra-panel interface addressing both low-power and low-EMI requirements for tablet PC applications is presented. The proposed interface features a novel function called scrambled transition-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d199fcf1e980f0dc88d822d6b2e83490
https://doi.org/10.1002/j.2168-0159.2014.tb00077.x
https://doi.org/10.1002/j.2168-0159.2014.tb00077.x
Autor:
Jung-Pil Lim, Gyoo-Cheol Hwang, Yoon Kyung Choi, Dong-Myung Lee, Wonho Tak, Kil-Hoon Lee, Hansu Pae, Jae-Youl Lee
Publikováno v:
SID Symposium Digest of Technical Papers. 45:283-285
This paper has reviewed several key features of intra-panel interfaces for high-resolution tablet personal computers to satisfy essential requirements such as high-speed operation, low power consumption, and low radio frequency interference (RFI). Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef3dc9747f93589c94231c124b872109
https://doi.org/10.1002/j.2168-0159.2014.tb00076.x
https://doi.org/10.1002/j.2168-0159.2014.tb00076.x
Autor:
Jae Youl Lee, Woo Sung Lee, Han Su Pae, Dong Hoon Baek, Yoon Kyung Choi, Young-hun Lee, Dae Joon Lee, Young-Min Choi, Jung Pil Lim, Myung Hee Lee, Sun Ik Lee, Wang Yu
Publikováno v:
SID Symposium Digest of Technical Papers. 41:70
The enhanced Reduced Voltage Differential Signaling eRVDS is a new intrapanel interface with clock embedded scheme for ChipOnGlass TFTLCD panel. The source driver IC with eRVDS interface operates at higher data rate up to 720Mbps, lower power consump
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be5f5f96f59eb1659e5990b18a945a7c
https://doi.org/10.1889/1.3500567
https://doi.org/10.1889/1.3500567
Publikováno v:
Journal of the Society for Information Display. 18:153
— Reduced-voltage differential signaling (RVDS) is a novel interface for TFT-LCD panels with a chip-on-glass (COG) structure, which has a point-to-point topology and a voltage mode differential signaling scheme. The voltage-driving interface scheme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6b3ac91bcf2aff9c141e739fe38547a
https://doi.org/10.1889/jsid18.2.153
https://doi.org/10.1889/jsid18.2.153
Publikováno v:
Smart Materials and Structures. 18:115024
A characteristic analysis of an ultrasonic motor (USM) at the design stage has thus far been impossible. Therefore, a characteristic analysis method is suggested on the basis of a proposed model describing the complex nonlinear contact condition betw
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1cd30452d38ec66d021c7dd98d100ddb
https://doi.org/10.1088/0964-1726/18/11/115024
https://doi.org/10.1088/0964-1726/18/11/115024
Autor:
Dong Hoon Baek, Woo Sung Lee, Myung Hee Lee, Jong-Seon Kim, Jae Wan Park, Tae Kyung Kim, Jae Youl Lee, Ji-Hoon Kim, Yoon Kyung Choi, Keun Ho Ryu, Young-Min Choi, Jae-chul Lee, Jong Hoon Hong, Jung Pil Lim, Paul Kim
Publikováno v:
SID Symposium Digest of Technical Papers. 40:959
Reduced Voltage Differential Signaling (RVDS) is a new interface for TFT-LCD panel with Chip-On-Glass (COG) structure which has point-to-point topology and voltage mode differential signaling scheme. The display source driver IC with RVDS interface p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e698251f8fc833d1b9bcb29d9f724862
https://doi.org/10.1889/1.3256957
https://doi.org/10.1889/1.3256957
Autor:
Jung-Pil Lim, Myunghee Lee, Ji-Hoon Kim, Hee-Young Seo, Ju-Hyun Ko, Yongjoo Song, Youngjin Cho, Ji-Woon Jung, Jong-Seon Kim, Jang-jin Nam, Kwanghee Lee, Beop-Hee Kim, Seongjong Yoo
Publikováno v:
SID Symposium Digest of Technical Papers. 39:882
A 720-channel LCD source driver with a 12-bit segmented R-C DAC has been designed and fabricated by a 16V CMOS process. The proposed DAC consists of a conventional resistor string and a sample-and-hold buffer. DNL less than 0.3LSB and output voltage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6337e8beb3223f35f123386080ae51f7
https://doi.org/10.1889/1.3069814
https://doi.org/10.1889/1.3069814