Výsledky vyhledávání

An Ultralow Power Time-Domain Temperature Sensor With Time-Domain Delta–Sigma TDC

Autor: Wonjong Song, Jinwook Burm, Nayeon Cho, Junan Lee

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 64:1117-1121

Without using bipolar transistors, serially connected inverter cells generate clock delay according to temperature. The delay is compared with a reference clock to estimate the temperature. The proposed time-to-digital converter (TDC) structure is us

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fef9e47c4983886667ef79d9353382bd
https://doi.org/10.1109/tcsii.2015.2503717

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High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

Autor: Kyunghoon Kim, Junan Lee, Kiwoon Kim, Jaeha Eom, Himchan Park, Jinwook Burm, Bongsub Song

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 62:2147-2155

This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6629124093e81c4332249bcbf92cecbb
https://doi.org/10.1109/tcsi.2015.2451791

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High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs

Autor: Kyunghoon Kim, Junan Lee, Jinwook Burm, Qiwei Huang, Kiwoon Kim

Publikováno v: JSTS:Journal of Semiconductor Technology and Science. 15:22-28

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SSADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the con

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d2151954df301a39fa38b1d195c1e9c3
https://doi.org/10.5573/jsts.2015.15.1.022

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A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13- $\mu\hbox{m}$ CMOS Technology

Autor: Junan Lee, Jinwook Burm, Bongsub Song, Young-Jung Choi, Jinil Chung, Kyunghoon Kim

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 61:646-650

A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It consists of voltage-scaled pull-up and pull-down networks, instead of c

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d8f03e890a8d2655ea98745fde6e4d93
https://doi.org/10.1109/tcsii.2014.2331101

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A behavioural modelling of nonlinear RF power amplifiers using noise compensation technique

Autor: Kwangsoo Kim, Kyunghoon Kim, Bongsub Song, Jung Han Choi, Junan Lee, Jinwook Burm

Publikováno v: International Journal of Electronics. 100:1675-1682

A nonlinear behavioural model of power amplifiers is proposed with an improved modelling method to fit up to the alternate channels where the noise contributions are dominant. From a memory polynomial model incorporating memory effects (Ku and Kenney

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::12e2a2e7f2864299254684e2a87fde94
https://doi.org/10.1080/00207217.2013.766909

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A fast AFC technique with self-calibration for fast-locking PLLs

Autor: Jinwook Burm, Bongsub Song, Junan Lee, Kyunghoon Kim

Publikováno v: International Journal of Electronics. 100:1080-1091

A fast adaptive frequency calibration (AFC) technique with self-calibration for fast-locking phase-locked loops is presented with frequency-selecting switches. The proposed AFC directly calculates the proper switch states of the voltage-controlled os

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6ec4fde59424371ab8e5386f509c1c95
https://doi.org/10.1080/00207217.2012.743064

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A 0.18-$\mu$m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

Autor: Junan Lee, Kyunghoon Kim, Jinwook Burm, Bongsub Song

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 60:457-468

A 0.18-μm CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2d6f7c977bf2b002e893a455c3d2ea11
https://doi.org/10.1109/tcsi.2012.2215799

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