Zobrazeno 1 - 10
of 173
pro vyhledávání: '"Jun-Sik Yoon"'
Autor:
Kihoon Nam, Chanyang Park, Hyeok Yun, Jun-Sik Yoon, Hyundong Jang, Kyeongrae Cho, Min Sang Park, Hyun-Chul Choi, Rock-Hyun Baek
Publikováno v:
IEEE Access, Vol 11, Pp 7135-7144 (2023)
A machine learning (ML) method was used to optimize the trap distribution of the charge trap nitride (CTN) to simultaneously improve its performance/reliability (P/R) characteristics, which are tradeoffs in 3-D NAND flash memories. Using an artificia
Externí odkaz:
https://doaj.org/article/3eb69a874bce4bdcbb11a9e92e3efa02
Autor:
Hyundong Jang, Hyeok Yun, Chanyang Park, Kyeongrae Cho, Kihoon Nam, Jun-Sik Yoon, Hyun-Chul Choi, Rock-Hyun Baek
Publikováno v:
IEEE Access, Vol 10, Pp 64408-64419 (2022)
We proposed a neural network (NN) approach that uses two multi-layer perceptron (MLP) NNs an encoder and a decoder to estimate the structural parameter (Spara) of a 14-nm node fully depleted silicon on insulator (FDSOI) field-effect transistor (FET).
Externí odkaz:
https://doaj.org/article/926c9966f6c34017acd794cba131d704
Autor:
Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Junjong Lee, Sanguk Lee, Jaewan Lim, Rock-Hyun Baek
Publikováno v:
IEEE Access, Vol 10, Pp 22032-22037 (2022)
Grain boundary (GB) at the source/drain (S/D) epitaxy was investigated using fully-calibrated TCAD. Because the S/D epi is grown separately at the bottom and the NS channels, nanosheet field-effect transistors (NSFETs) have unwanted GB within the S/D
Externí odkaz:
https://doaj.org/article/376710b9e59a43abb680aeff5772f010
Autor:
Dan Kim, Jun-Young Jung, Hyun-Seok Oh, Sam-Ryong Jee, Sung Jae Park, Sang-Heon Lee, Jun-Sik Yoon, Seung Jung Yu, In-Cheol Yoon, Hong Sub Lee
Publikováno v:
BMC Gastroenterology, Vol 21, Iss 1, Pp 1-13 (2021)
Abstract Background Dysbiosis of ulcerative colitis (UC) has been frequently investigated using readily accessible stool samples. However, stool samples might insufficiently represent the mucosa-associated microbiome status. We hypothesized that lumi
Externí odkaz:
https://doaj.org/article/867097b430d245479b6e0077005d7d95
Publikováno v:
Nanomaterials, Vol 13, Iss 9, p 1451 (2023)
The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three−dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme
Externí odkaz:
https://doaj.org/article/4be4beb601574daca9bb9298ecd457d9
Publikováno v:
IEEE Access, Vol 9, Pp 16728-16735 (2021)
Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneou
Externí odkaz:
https://doaj.org/article/acf36e80602f464ba02dcb1b8752cd32
Publikováno v:
IEEE Access, Vol 9, Pp 29071-29077 (2021)
Vertical nanowire field-effect transistors (NWFETs) have been optimized to maximize digital and analog performances using fully-calibrated TCAD and machine learning (ML) technique. Digital performance is quantified by RC delay (CggVdd/Ion, where Cgg
Externí odkaz:
https://doaj.org/article/c47ba7a692184a51a864dc70fee238a6
Publikováno v:
IEEE Access, Vol 9, Pp 138192-138199 (2021)
For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAMSDGBC) and analyzed they could significantly improve the power, performance, and area (PPA)
Externí odkaz:
https://doaj.org/article/bca9431751f1470ea8f23037fbb1d625
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1272-1280 (2020)
In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (
Externí odkaz:
https://doaj.org/article/2aa003866b30422bb204d4dfb7416891
Publikováno v:
IEEE Access, Vol 8, Pp 35873-35881 (2020)
Excess source and drain (S/D) recess depth (TSD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-
Externí odkaz:
https://doaj.org/article/dd3149784d574df689e44143c42e1a3f