Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Juma Mary Atieno"'
Publikováno v:
The Journal of Engineering (2017)
Through silicon via (TSV) interconnect reliability is a problem in electronic packaging. The authors address the insertion losses, deflections which can result to separation of TSV layers and hoop stresses. These problems are due to different coeffic
Externí odkaz:
https://doaj.org/article/24599911df0f4d2ca5aa8949fd2088b6
Publikováno v:
Advances in Science, Technology and Engineering Systems, Vol 2, Iss 3, Pp 268-276 (2017)
Segmented and unsegmented 3D insulated copper through silicon vias (TSVs) of diameter 10 micro-meter, height 100 micro-meter and silicon of sizes 100 micro-meter by 100 micro-meter by 100 micro-meter are modeled using analysis system (ANSYS), equival
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fc287175e6c477df799e3da1b761a65c
https://astesj.com/v02/i03/p36/
https://astesj.com/v02/i03/p36/
Autor:
Zhang Xuliang, Juma Mary Atieno
Publikováno v:
IOSR Journal of Electrical and Electronics Engineering. 9:20-25
One of the most common forms of failures observed in flipchips brittle thin films subjected to stress is cracking. The crack growth rate depends on intrinsic film properties, stress and some environmental factors. In part 1 of this paper, we investig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cdef130a891b88b56dbfd5f8dd423f1e
https://doi.org/10.9790/1676-09212025
https://doi.org/10.9790/1676-09212025
Publikováno v:
2016 International Conference on Integrated Circuits and Microsystems (ICICM).
A segmented and unsegmented 3D insulated copper through silicon vias (TSVs) of diameter 10μm, height 100μm and silicon of sizes 100μm by 100μm by 100μm are modelled using analysis system (ANSYS) and equivalent circuit using advanced design syste
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf7f5cdc97596e1586dd4652c3e2c1b2
https://doi.org/10.1109/icam.2016.7813598
https://doi.org/10.1109/icam.2016.7813598
Publikováno v:
2015 IEEE Advanced Information Technology, Electronic and Automation Control Conference (IAEAC).
Through Silicon Via Interconnects are usually protected with liners. A research on liners was done and conclusion made that they experience reliability problems like hoop stress which put them and the Through Silicon Via in danger. Simulation using A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04db8e5749c98ac975d84ab127c7320a
https://doi.org/10.1109/iaeac.2015.7428601
https://doi.org/10.1109/iaeac.2015.7428601
Publikováno v:
Proceedings of the 2015 Joint International Mechanical, Electronic and Information Technology Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23c132357377986ed258f81928e0e2ef
https://doi.org/10.2991/jimet-15.2015.205
https://doi.org/10.2991/jimet-15.2015.205
Autor:
Zhang Xuliang, Juma Mary Atieno
Publikováno v:
Control Engineering and Electronics Engineering.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eee5fb6b4d779b9f2fcff3ef8cbf0aee
https://doi.org/10.2495/cceee140401
https://doi.org/10.2495/cceee140401
Autor:
Verikas, Antanas, Radeva, Petia, Nikolaev, Dmitry, Juma, Mary Atieno, Zhang, Xuliang, He, Song Bai, Abusabah, Ahmed I. A.
Publikováno v:
Proceedings of SPIE; December 2015, Vol. 9875 Issue: 1 p987528-987528-5