Zobrazeno 1 - 10
of 159
pro vyhledávání: '"Julio Sahuquillo"'
Publikováno v:
Journal of Big Data, Vol 11, Iss 1, Pp 1-29 (2024)
Abstract The microarchitecture of general-purpose processors is continuously evolving to adapt to the new computation and memory demands of incoming workloads. In this regard, new circuitry is added to execute specific instructions like vector multip
Externí odkaz:
https://doaj.org/article/c6344b498bea43de814de180f94acfe7
Autor:
Miguel A. Avargues, Manel Lurbe, Salvador Petit, Maria E. Gomez, Rui Yang, Xiaoping Zhu, Guanhao Wang, Julio Sahuquillo
Publikováno v:
Journal of Big Data, Vol 10, Iss 1, Pp 1-19 (2023)
Abstract SRAM and DRAM memory technologies have been dominant in the implementations of memory subsystems. In recent years, and mainly driven by the huge memory demands of big data applications, NVRAM technology has emerged as a denser memory technol
Externí odkaz:
https://doaj.org/article/bb7ffe324fd443c38ca90099ebb258a3
Publikováno v:
IEEE Access, Vol 9, Pp 43095-43106 (2021)
Photonics are becoming realistic technologies for implementing interconnection networks in near future Exascale supercomputer systems. Photonics present key features to design high-performance and scalable supercomputer networks, such as higher bandw
Externí odkaz:
https://doaj.org/article/1f60012a28a943dabd2286ef357a07d0
Publikováno v:
CLEI Electronic Journal, Vol 15, Iss 2 (2012)
The evolution of the World Wide Web from hypermedia information repositories to web applications such as social networking, wikis or blogs has introduced a new paradigm where users are no longer passive web consumers. Instead, users have become activ
Externí odkaz:
https://doaj.org/article/d94e0077afa743de8e8a904397a54217
Autor:
Lucía Pons, Josué Feliu, Julio Sahuquillo, María E. Gómez, Salvador Petit, Julio Pons, Chaoyi Huang
Publikováno v:
Future Generation Computer Systems. 138:13-25
Publikováno v:
IEEE Transactions on Computers. 71:2646-2658
Autor:
Lucía Pons, Josué Feliu, José Puche, Chaoyi Huang, Salvador Petit, Julio Pons, María E. Gómez, Julio Sahuquillo
Publikováno v:
Future Generation Computer Systems. 131:194-208
Publikováno v:
Proceedings of the 51st International Conference on Parallel Processing.
Publikováno v:
2022 30th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).
Publikováno v:
RiuNet: Repositorio Institucional de la Universitat Politécnica de Valéncia
Universitat Politècnica de València (UPV)
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
Universitat Politècnica de València (UPV)
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
[EN] The cache hierarchy of current multicores typically consists of three levels, ranging from the faster and smaller L1 level to the slower and larger L3 level. This approach has been demonstrated to be effective in high performance processors, sin