Zobrazeno 1 - 10
of 353
pro vyhledávání: '"Julio Sahuquillo"'
Publikováno v:
Journal of Big Data, Vol 11, Iss 1, Pp 1-29 (2024)
Abstract The microarchitecture of general-purpose processors is continuously evolving to adapt to the new computation and memory demands of incoming workloads. In this regard, new circuitry is added to execute specific instructions like vector multip
Externí odkaz:
https://doaj.org/article/c6344b498bea43de814de180f94acfe7
Autor:
Miguel A. Avargues, Manel Lurbe, Salvador Petit, Maria E. Gomez, Rui Yang, Xiaoping Zhu, Guanhao Wang, Julio Sahuquillo
Publikováno v:
Journal of Big Data, Vol 10, Iss 1, Pp 1-19 (2023)
Abstract SRAM and DRAM memory technologies have been dominant in the implementations of memory subsystems. In recent years, and mainly driven by the huge memory demands of big data applications, NVRAM technology has emerged as a denser memory technol
Externí odkaz:
https://doaj.org/article/bb7ffe324fd443c38ca90099ebb258a3
Publikováno v:
IEEE Access, Vol 9, Pp 43095-43106 (2021)
Photonics are becoming realistic technologies for implementing interconnection networks in near future Exascale supercomputer systems. Photonics present key features to design high-performance and scalable supercomputer networks, such as higher bandw
Externí odkaz:
https://doaj.org/article/1f60012a28a943dabd2286ef357a07d0
Autor:
Lucía Pons, Josué Feliu, Julio Sahuquillo, María E. Gómez, Salvador Petit, Julio Pons, Chaoyi Huang
Publikováno v:
Future Generation Computer Systems. 138:13-25
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::125bcad897d27c2a663fa50ad345dfda
https://doi.org/10.1016/j.future.2022.08.012
https://doi.org/10.1016/j.future.2022.08.012
Publikováno v:
IEEE Transactions on Computers. 71:2646-2658
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04f95cd12ab3bcf7c0142e58bd79bfbe
https://doi.org/10.1109/tc.2021.3139997
https://doi.org/10.1109/tc.2021.3139997
Autor:
Lucía Pons, Josué Feliu, José Puche, Chaoyi Huang, Salvador Petit, Julio Pons, María E. Gómez, Julio Sahuquillo
Publikováno v:
Future Generation Computer Systems. 131:194-208
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48d87c4e8f7b6c5735e1da0da460f911
https://doi.org/10.1016/j.future.2022.01.025
https://doi.org/10.1016/j.future.2022.01.025
Publikováno v:
Proceedings of the 51st International Conference on Parallel Processing.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0daa8061bf7cb828cf894cc4abe1ee56
https://doi.org/10.1145/3545008.3545083
https://doi.org/10.1145/3545008.3545083
Publikováno v:
2022 30th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8536676a9420e93a30b2ece9572411d9
https://doi.org/10.1109/pdp55904.2022.00018
https://doi.org/10.1109/pdp55904.2022.00018
Publikováno v:
RiuNet: Repositorio Institucional de la Universitat Politécnica de Valéncia
Universitat Politècnica de València (UPV)
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
Universitat Politècnica de València (UPV)
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
[EN] The cache hierarchy of current multicores typically consists of three levels, ranging from the faster and smaller L1 level to the slower and larger L3 level. This approach has been demonstrated to be effective in high performance processors, sin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f7384ad2c9e94e36e315b4df53b76ca5
https://doi.org/10.1016/j.future.2019.11.024
https://doi.org/10.1016/j.future.2019.11.024
Autor:
Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Matteo Turisini, Piero Vicini, Roberto Ammendola, Pascale Bernier-Bruna, Claire Chen, Said Derradji, Stephane Guez, Pierre-Axel Lagadec, Gregoire Pichon, Etienne Walter, Gaetan De Gassowski, Matthieu Hautreaux, Stephane Mathieu, Gilles Moreau, Marc Perache, Hugo Taboada, Torsten Hoefler, Timo Schneider, Matteo Barnaba, Giuseppe Piero Brandino, Francesco De Giorgi, Matteo Poggi, Iakovos Mavroidis, Yannis Papaefstathiou, Nikolaos Tampouratzis, Benjamin Kalisch, Ulrich Krackhardt, Mondrian Nuessle, Pantelis Xirouchakis, Vangelis Mageiropoulos, Michalis Gianioudis, Harisis Loukas, Aggelos Ioannou, Nikos Kallimanis, Nikos Chrysos, Manolis Katevenis, Wolfang Frings, Dominik Gottwald, Felime Guimaraes, Max Holicki, Volker Marx, Yannik Muller, Carsten Clauss, Hugo Falter, Xu Huang, Jennifer Lopez Barillao, Thomas Moschny, Simon Pickartz, Francisco J. Alfaro, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Jose L. Sanchez, Adrian Castello, Jose Duro, Maria Engracia Gomez, Enrique Quintana, Julio Sahuquillo, Eugenio Stabile
Publikováno v:
2022 25th Euromicro Conference on Digital System Design (DSD)
In order to enable Exascale computing, next generation interconnection networks must scale to hundreds of thousands of nodes, and must provide features to also allow the HPC, HPDA, and AI applications to reach Exascale, while benefiting from new hard
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::180f713f306e6611b046d052542a4cac
https://hdl.handle.net/20.500.11850/605842
https://hdl.handle.net/20.500.11850/605842
