Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Julien De-Vos"'
Autor:
Marcel Meli, Oskar Vujicic, Mathieu Bellanger, Denis Pasero, Matthias Kauer, Dimitrios Tzovaras, Charalampos S. Kouzinopoulos, Martin Schellenberg, Julien De Vos, Pawel Bembnowicz
Publikováno v:
2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)
ICCE-Berlin
ICCE-Berlin
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0449dae363fa8741e52367884f217390
https://hdl.handle.net/11475/20058
https://hdl.handle.net/11475/20058
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:1597-1606
This paper proposes a systematic sizing methodology for switched-capacitor DC/DC converters aimed at maximizing the converter efficiency under the die area constraint. To do so, we propose first an analytical solution of the optimum switching frequen
Publikováno v:
Journal of Low Power Electronics. 8:95-112
In this paper, we investigate the possibility for low-power applications to integrate an efficient Adaptive Voltage Scaling (AVS) system on chip. Therefore the impact of process (both global and local), voltage and temperature variations is firstly s
Publikováno v:
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
Ultra-Low-Voltage (ULV) System-on-a-Chips (SoCs) are a growing research interest to fulfil the energy efficiency requirements of the wireless sensor node applications featuring sleep power below 1iXW. ULP mixed-signal SoCs require a voltage reference
Publikováno v:
ESSCIRC
We propose an energy-harvesting management unit to interface a PV harvester with a storage supercapacitor while generating a 1V regulated supply VREG. Direct connection between stacked PV cells and VREG allows virtual 100% conversion efficiency betwe
Autor:
Pierre Schamberger, Fady Abouzeid, Martin Cochet, Mehdi Saligane, Dennis Sylvester, Dominique Zamora, Benjamin Coeffic, Cyril Bottoni, Julien De-Vos, Philippe Roche, Jean-Marc Daveau, Mehdi Naceur, Damien Croain, David Bol, Sylvain Clerc, Dimitri Soussan
Publikováno v:
ISSCC
A 32b SoC is designed in 28nm FDSOI to operate in either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) mode, at 0.33V, with process-temperature compensation. At near threshold, it overcomes low transistor current at negative temperatu
Publikováno v:
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
Total ionizing dose (TID) jeopardizes the operation of ULV circuits by shifting the threshold voltage of the devices. Measurements on a 65nm SoC show that it modifies the output of an on-chip 4-T voltage reference by 3.5% and the gate delay at ULV by
Autor:
François Botman, David Bol, Sebastien Bernard, Julien De Vos, Jean-Didier Legat, Francois Stas
Publikováno v:
ISCAS
In the context of wireless sensor nodes for the Internet-of-Things, there is a need for low-power high-performance computing cores for video monitoring applications. In this paper we present a custom 50MHz 32-bit microcontroller running at 0.37V buil
Publikováno v:
2014 IEEE Faible Tension Faible Consommation.
A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V outp
Publikováno v:
2014 IEEE Faible Tension Faible Consommation.
The development of wireless sensor nodes (WSNs) as well as the rise of the Internet-of-Things (IoT) push ahead the research effort in ultra-low-power integrated circuits. Jointly with the recent development of micro-energy harvesters, it extends the