Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Jue Hsuan Hsiao"'
Publikováno v:
SSD
This study referenced the approximate lower triangular code check matrix in the low density parity check code of IEEE P802.11n™/D1.04 (Part 11: Wireless LAN Medium Access Control). The matrix was written in the LabVIEW programming language. Using a
Publikováno v:
IEEE Transactions on Signal Processing. 45:2140-2144
A bit-level pipelined VLSI architecture for the running order algorithm is presented. Based on the proposed modified algorithm, the deletion and the insertion is successfully pipelined in the bit-level operation. A block processing architecture of th
Publikováno v:
IEEE Transactions on Consumer Electronics. 42:33-42
The VLSI implementation of a selective median filter for real-time applications is presented. The proposed design is based on a novel bit-level running algorithm with a modular and parallel structure. A chip designed by the cell-based style is demons
Publikováno v:
ISCAS
Scopus-Elsevier
Scopus-Elsevier
We propose a modified fast algorithm for discrete cosine transform (DCT) by transferring the results from the discrete Hartley transform (DHT) to one additional CORDIC (coordinate rotation digital computer) computing stage. A fast CORDIC-based systol
Publikováno v:
The 1st IEEE Global Conference on Consumer Electronics 2012.
This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed
Publikováno v:
2011 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC).
This work demonstrates the implementation of high-performance visual IP generator for High Pass (HP) filter using Microsoft Visual Studio 2008. The sum of multiple constant coefficient multiplications (MCM) is the major part in the HP filter. In the
Publikováno v:
2011 11th International Conference on ITS Telecommunications.
This work demonstrates the implementation of visual IP generator for Square Root Raised Cosine (SRRC) filter based on Microsoft Visual Studio 2008. The sum of coefficient product terms is the major part in the SRRC filter. In the Visual IP Generator,
Publikováno v:
Proceedings of 2011 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference.
This work demonstrates the implementation of high-performance visual IP generator for Low Pass (LP) filter using Microsoft Visual Studio 2008. The sum of coefficient product terms is the major part in the LP filter. In the Visual IP Generator, we pro
Publikováno v:
2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).
This study discussed the decoding mechanism of block product turbo code (BPTC) (196,96) and analyzed its efficiency, used the Hamming (15,11) and Hamming (13,9) block channel code combinations and block interleaving to construct a BPSK modulation and
Publikováno v:
2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).
This study analyzed and simulated special Golay (20, 8) channel code. When the bit error probability P b = 10−5, Hamming (16, 11) has about 0.5dB coding gain compared with Golay Code (20,8) t = 3, and Golay Code (20,8) t = 4 has about 0.2dB coding