Fast IEEE802.1Qbv Gate Scheduling Through Integer Linear Programming

Autor: Alitzel Galilea Torres-Macias, Juan Segarra Flor, Jose Luis Briz Velasco, Antonio Ramirez-Trevino, Hector Blanco-Alcaine

Publikováno v: IEEE Access, Vol 12, Pp 111239-111250 (2024)

Time-Sensitive Networking (TSN) is an in-development technology that enables predictability over Ethernet or wireless networks. Network interfaces compliant with the IEEE 802.1Qbv standard provide different queues/gates on each bridge egress port. In

Externí odkaz: https://doaj.org/article/f95f9970a7ff431eac2d23bbdd946f1f

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

Autor: Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Victor Vinals-Yufera

Publikováno v: IEEE Access, Vol 8, Pp 192379-192392 (2020)

Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in orde

Externí odkaz: https://doaj.org/article/68ada3df74354463ade76464f7a179d6

Ideal and Predictable Hit Ratio for Matrix Transposition in Data Caches

Autor: Alba Pedro-Zapater, Clemente Rodríguez, Juan Segarra, Rubén Gran Tejero, Víctor Viñals-Yúfera

Publikováno v: Mathematics, Vol 8, Iss 2, p 184 (2020)

Matrix transposition is a fundamental operation, but it may present a very low and hardly predictable data cache hit ratio for large matrices. Safe (worst-case) hit ratio predictability is required in real-time systems. In this paper, we obtain the r

Externí odkaz: https://doaj.org/article/48838d70bce64484a73455915d0935e4

'Desdisciplinar a antropologia': diálogo com eduardo restrepo

Autor: Ondina Fachel Leal, Patrice Schuch, Denise Fagundes Jardim, Marcela Velásquez Cuartas, Tomás Guzmán Sánchez, Alex Martins Moraes, Josep Juan Segarra

Publikováno v: Horizontes Antropológicos, Vol 20, Iss 41, Pp 359-379 (2014)

Externí odkaz: https://doaj.org/article/18cae0ac81734dfdadb40436ecfb4b71

Reducing the WCET and analysis time of systems with simple lockable instruction caches

Autor: C. Rodriguez, Ruben Gran Tejero, Víctor Viñals, Alba Pedro-Zapater, Juan Segarra

Publikováno v: PLoS ONE
Addi. Archivo Digital para la Docencia y la Investigación
instname
PLoS ONE, Vol 15, Iss 3, p e0229980 (2020)
Zaguán: Repositorio Digital de la Universidad de Zaragoza
Universidad de Zaragoza
Zaguán. Repositorio Digital de la Universidad de Zaragoza

One of the key challenges in real-time systems is the analysis of the memory hierarchy. Many Worst-Case Execution Time (WCET) analysis methods supporting an instruction cache are based on iterative or convergence algorithms, which are rather slow. Ou

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c4e22fae8b59d2126824170562f365b9
http://hdl.handle.net/10810/42576