Zobrazeno 1 - 1
of 1
pro vyhledávání: '"Juan Renteria-Cedano"'
Publikováno v:
Electronics, Vol 8, Iss 7, p 761 (2019)
Electronics
Volume 8
Issue 7
Electronics
Volume 8
Issue 7
This work presents a configurable architecture for an artificial neural network implemented with a Field Programmable Gate Array (FPGA) in a System on Chip (SoC) environment. This architecture can reproduce the transfer function of different Multilay
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3bff3f0b55b4ddecaf2bfb14ced1eac4
https://www.mdpi.com/2079-9292/8/7/761
https://www.mdpi.com/2079-9292/8/7/761
