Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Ju-Il Choi"'
Autor:
Se-Chul Park, Jong-Ho Park, Seonghoon Bae, Junyoung Park, Taehwa Jung, Hyojin Yun, Kwangok Jeong, Seok-Bong Park, Ju-Il Choi, Un-Byoung Kang, Dongwoo Kang
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0e5899a36f95836b4e13103762c8cba
https://doi.org/10.1109/ectc51906.2022.00164
https://doi.org/10.1109/ectc51906.2022.00164
Autor:
Jongho Lee, Jum-Yong Park, Un-Byoung Kang, Hyunsu Hwang, Chung-Sun Lee, Ju-Il Choi, Jeongi Jin, Gyuho Kang, Byungchan Kim, Hyo-Jin Yun
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Fan-out Wafer Level Packaging (FOWLP) is expected to become an indispensable platform for integrating heterogeneous chips into advanced semiconductor packaging for next generation edge computing, automotive and others. In order to integrate multiple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0d4e8476a784c4d7bcb57ae2a192394
https://doi.org/10.1109/ectc32696.2021.00352
https://doi.org/10.1109/ectc32696.2021.00352
Autor:
Jeon Gwangjae, Seok Hyun Lee, Ju-Il Choi, Won Kyoung Choi, Kyoung Lim Suk, Hyo Jin Yun, Sukhyun Jung, Jae Gwon Jang, Jongpa Hong, Dae-Woo Kim, Ju-Yeon Choi, Wonjae Lee, Min Jung Kim
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Advances in the high performance computing (HPC) lead to a new frontier of the fan out wafer level packaging (FOWLP) development. To provide a solution of cost-attractive package for heterogeneous chip integration, FOWLP has recently emerged as an in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d0a15d07e3d746f9c66d48f8ad1008de
https://doi.org/10.1109/ectc32696.2021.00061
https://doi.org/10.1109/ectc32696.2021.00061
Autor:
H.-S. Oh, Lee Kihuk, Seungseob Lee, Yoon-dong Park, Chang Seok Lee, Tae-Kyung Kim, Ju-Il Choi, Dong-Yean Oh, Junjin Kong, Jai-Hyuk Song
Publikováno v:
Symposium Non-Volatile Memory Technology 2005..
The cell string current of NAND flash memory is very small due to large resistance from the cells connected in series. In this paper, scaling effects on the cell current are analyzed for 70/60/50 nm NAND flash technologies using 3-dimensional TCAD si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::175f77bb02d57a1565271a668ad7887b
https://doi.org/10.1109/nvmt.2005.1541422
https://doi.org/10.1109/nvmt.2005.1541422
Autor:
B.J. Hwang, Kun-Ho Kwak, Jung-hyeon Kim, Sae-jin Kim, Wouns Yang, S. H. Park, Myeong-cheol Kim, Sunae Seo, Ju-Il Choi, D.H. Kim, J.Y. Lee, Kyoung-Min Koh, Jun-Ki Hong, Hyung-Rae Lee, Joon-Yong Joo
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38aec751427fb13f14dba9261e322733
https://doi.org/10.1109/vlsit.2002.1015416
https://doi.org/10.1109/vlsit.2002.1015416