Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Joung-Wook Moon"'
Autor:
Daesik Moon, Jung-Hwan Choi, Seok-Hun Hyun, Jung-Bae Lee, Sung-Woo Yoon, Su-Jin Park, Dong-Hoon Lee, Jin-Hyeok Baek, Seung-Jun Bae, Y.S. Park, Hui-Kap Yang, Ki-Han Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Chang-Kyo Lee, Bok-Gue Park, Young-Jae Kim, Jin-Seok Heo, Kyungryun Kim, Soobong Jang, Ki-Ho Kim, Joung-Wook Moon, Kwang-Il Park, Jae-Hyung Lee
Publikováno v:
VLSI Circuits
A 5Gb/s/pin 16Gb LPDDR4/4X reconfigurable SDRAM with a self-mode detection scheme, a voltage-high keeper (VHK) for un-terminated load and a prediction-based fast-tracking ZQ algorithm is implemented in 10nm class ($2^{nd}$ generation) DRAM process. P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3570d22e6ced3e4156d6ecfd888ad57d
https://doi.org/10.23919/vlsic.2019.8778102
https://doi.org/10.23919/vlsic.2019.8778102
Autor:
Young-Soo Sohn, Joung-Wook Moon, Dong-Hun Lee, Haeyoung Chung, Seok-Yong Kang, Seong-Jin Jang, Jun-Bae Kim, Yong-Ho Cho, Ki-Ho Kim, In-Dal Song, Kwang-Il Park, Hundai Choi, Jung-Hwan Choi, Hye-Sung Yoo, Seok-Hun Hyun, Il-Won Park, Ki-Jae Song
Publikováno v:
A-SSCC
This paper presents a wide-frequency-range, self-calibrating, built-off-test (BOT) transceiver for a DDR4 SDRAM interface. The proposed BOT transceiver consists of a data transceiver, a phase-locked loop, a delay-locked loop, a self-timing calibratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c643084e66fe95f71eb2fcf04a50c308
https://doi.org/10.1109/asscc.2018.8579329
https://doi.org/10.1109/asscc.2018.8579329
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 61:319-323
A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bbdd6bc20e8f45e7d6306ce7c056eb20
https://doi.org/10.1109/tcsii.2014.2312800
https://doi.org/10.1109/tcsii.2014.2312800
Autor:
Min-Soo Jang, Joung-Wook Moon, Young-Hyun Jun, Hyunyoon Cho, Hanna Park, Ho-Young Kim, Jong-Min Bang, Hyong-Ryol Hwang, Joo-Sun Choi, Jin-Guk Kim, Sang-Kyu Kang, Jung-Bae Lee, Ho-Cheol Lee, Sooman Hwang, Jung-Sik Kim, Donghyuk Lee, Cheolmin Han, Ki-Won Park, Byongwook Na, So-Young Kim, Kye-Hyun Kyung, Chi Sung Oh, Jang-Woo Ryu
Publikováno v:
ISSCC
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify fu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4a93d80e07a726da5ebd37c33ab3067
https://doi.org/10.1109/jssc.2011.2164731
https://doi.org/10.1109/jssc.2011.2164731
Publikováno v:
CICC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d154ee7cad93a47664ba71317152c07
https://doi.org/10.1109/cicc.2014.6946100
https://doi.org/10.1109/cicc.2014.6946100