Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Joshua M. Lucas"'
Publikováno v:
Microprocessors and Microsystems. 30:445-456
The growing complexity of Field Programmable Gate Arrays (FPGA’s) is leading to architectures with high input cardinality look-up tables (LUT’s). This paper describes a methodology for area-optimal combinational technology mapping, specifically d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::043535aac96c75e6b2cfed449084ff4e
https://doi.org/10.1016/j.micpro.2006.04.002
https://doi.org/10.1016/j.micpro.2006.04.002
Autor:
Brady Hunsaker, Justin Stander, Gayatri Mehta, Alex K. Jones, Raymond R. Hoare, Joshua M. Lucas
Publikováno v:
Journal of Low Power Electronics. 2:148-164
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87d96579e6ce0949929151d016d1dfb6
https://doi.org/10.1166/jolpe.2006.073
https://doi.org/10.1166/jolpe.2006.073
Publikováno v:
FCCM
This paper describes an inexact string matching scheme devised to improve upon the LURU technique. The scheme uses a set of text strings called common subcircuit expressions (CSEs) to map a high percentage of the subcircuits in a netlist. The inexact
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::000ea52606a5009364c082233d194c88
https://doi.org/10.1109/fccm.2005.50
https://doi.org/10.1109/fccm.2005.50
Publikováno v:
ICECS
The paper proposes a technique for area-optimized FPGA technology mapping. The LURU algorithm maps a combinational circuit to a network of K-input lookup tables (LUTs). The LURU algorithm uses content addressable memory (CAM) to enable parallel patte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff6983e1e9282bd7624a84a7465d429b
https://doi.org/10.1109/icecs.2004.1399752
https://doi.org/10.1109/icecs.2004.1399752