Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Joshua M. Lucas"'
Publikováno v:
Microprocessors and Microsystems. 30:445-456
The growing complexity of Field Programmable Gate Arrays (FPGA’s) is leading to architectures with high input cardinality look-up tables (LUT’s). This paper describes a methodology for area-optimal combinational technology mapping, specifically d
Autor:
Brady Hunsaker, Justin Stander, Gayatri Mehta, Alex K. Jones, Raymond R. Hoare, Joshua M. Lucas
Publikováno v:
Journal of Low Power Electronics. 2:148-164
Publikováno v:
FCCM
This paper describes an inexact string matching scheme devised to improve upon the LURU technique. The scheme uses a set of text strings called common subcircuit expressions (CSEs) to map a high percentage of the subcircuits in a netlist. The inexact
Publikováno v:
ICECS
The paper proposes a technique for area-optimized FPGA technology mapping. The LURU algorithm maps a combinational circuit to a network of K-input lookup tables (LUTs). The LURU algorithm uses content addressable memory (CAM) to enable parallel patte
Publikováno v:
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 2006, pv-x, 6p
Publikováno v:
Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits & Systems, 2004 (ICECS 2004); 2004, p599-602, 4p
Publikováno v:
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05); 2005, p293-294, 2p
Autor:
Michael J. Gerhardt
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