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pro vyhledávání: '"Joseph Rabinowicz"'
Autor:
Joseph Rabinowicz, Shlomo Greenberg
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 11, Iss 3, p 35 (2021)
This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Pow
Externí odkaz:
https://doaj.org/article/724a9de6f49f43f097880e6572fcb7f6
Autor:
Shlomo Greenberg, Joseph Rabinowicz
Publikováno v:
Journal of Low Power Electronics and Applications
Volume 11
Issue 3
Journal of Low Power Electronics and Applications, Vol 11, Iss 35, p 35 (2021)
Volume 11
Issue 3
Journal of Low Power Electronics and Applications, Vol 11, Iss 35, p 35 (2021)
This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Pow
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:807-815
This work is aimed to reduce the area and power consumption in low-power VLSI design. A new selective approach for State Retention Power Gating (SRPG) based on Module Checking formal verification techniques is presented, and so-called Selective SRPG
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:1095-1104
This work presents a novel approach based on gate-level analysis for implementing Selective State Retention Power Gating (SSRPG). A selective SRPG approach mitigates the area and power overhead of the conventional SRPG technique. However, only very f