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pro vyhledávání: '"Joseph C. Kerekes"'
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Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible na
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8b1fd17c85f695cfff0d438e8a401116
https://doi.org/10.1145/1555815.1555809
https://doi.org/10.1145/1555815.1555809
Autor:
WERNER, SEBASTIAN1 (AUTHOR) sebastian.werner@manchester.ac.uk, NAVARIDAS, JAVIER1 (AUTHOR) javier.navaridas@manchester.ac.uk, LUJÁN, MIKEL1 (AUTHOR) mikel.lujan@manchester.ac.uk
Publikováno v:
ACM Computing Surveys. Nov2018, Vol. 50 Issue 6, p1-37. 37p.
Publikováno v:
ACM Journal on Emerging Technologies in Computing Systems; May2017, Vol. 13 Issue 4, p1-25, 25p
Publikováno v:
On-Chip Photonic Interconnects; 2013, p77-90, 14p
Publikováno v:
2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops & Phd Forum; 2013, p649-658, 10p
Publikováno v:
Proceedings of the 36th Annual International Symposium: Computer Architecture; 6/20/2009, p441-450, 10p
Publikováno v:
ACM Journal on Emerging Technologies in Computing Systems; May2014, Vol. 10 Issue 4, p29:1-29:25, 25p
As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of proces
As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of proces