Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Josef Strnadel"'
Autor:
Josef Strnadel
Publikováno v:
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd598ef19fce810e8d7c27f6a93287fe
https://doi.org/10.1109/ddecs54261.2022.9770166
https://doi.org/10.1109/ddecs54261.2022.9770166
Autor:
Josef Strnadel
Publikováno v:
DDECS
Narrow timing margins in modern digital circuits result in delay defects that are difficult to detect. The probability that such a defect occurs increases with factors such as shrinking feature sizes, increasing process variations, operating frequenc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75afad87b016ac09e525cd5a4ae04e98
https://doi.org/10.1109/ddecs52668.2021.9417069
https://doi.org/10.1109/ddecs52668.2021.9417069
Autor:
Josef Strnadel
Publikováno v:
DATE
Many works have shown that approximate circuits may play an important role in the development of resource-efficient electronic systems. This motivates many researchers to propose new approaches for finding an optimal trade-off between the approximati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b99b6ae75cced7e5b4e856bdd74a8005
https://doi.org/10.23919/date48585.2020.9116207
https://doi.org/10.23919/date48585.2020.9116207
Autor:
Josef Strnadel
Publikováno v:
IEEE Design & Test. 35:57-63
This article proposes a model comprising of a network of stochastic timed automata for predictability analysis of interruptible systems via statistical model checking.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebb0a6d8e681dbfe0ed5cfe1f57aae1f
https://doi.org/10.1109/mdat.2017.2766568
https://doi.org/10.1109/mdat.2017.2766568
Autor:
Josef Strnadel
Publikováno v:
DATE
Ideally, the reliability can be assessed analytically, provided that an analytical solution exists and its presumptions are met. Otherwise, alternative approaches to the assessment must apply. This paper proposes a novel, simulation based approach th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f90543a85ded42cc6776787e6c468b88
https://doi.org/10.23919/date.2019.8714878
https://doi.org/10.23919/date.2019.8714878
Autor:
Josef Strnadel
Publikováno v:
DSD
The problem of dependability assessment can be solved analytically just under predefined conditions. If they do not hold, alternative approaches must apply. Widely, they rely on the Monte Carlo simulation, suffering by the high computational complexi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c59d6c8051ab1f561dddca7310733d7
https://doi.org/10.1109/dsd.2017.12
https://doi.org/10.1109/dsd.2017.12
Autor:
Josef Strnadel
Publikováno v:
Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques ISBN: 9783319471655
ISoLA (1)
ISoLA (1)
The paper presents a method for creation and analysis of reliability models by means of stochastic timed automata and statistical model checking approach available in the UPPAAL SMC tool; its application is expected in, but not limited to, the area o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df5b113c5f29455466280e97cb36e5b5
https://doi.org/10.1007/978-3-319-47166-2_11
https://doi.org/10.1007/978-3-319-47166-2_11
Autor:
Josef Strnadel
Publikováno v:
ECBS-EERC
This paper is related to event-driven embedded systems whose function can be divided into the real-time (RT) and non-RT parts. Such a system must be designed so that all predetermined timing constraints are met at runtime, even in adverse conditions
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d2b94004b9370aaffb315c5f04759fa
https://doi.org/10.1109/ecbs-eerc.2015.15
https://doi.org/10.1109/ecbs-eerc.2015.15
Autor:
Josef Strnadel, František Slimařík
Publikováno v:
COMPUTING AND INFORMATICS; Vol 33, No 4 (2014): Computing and Informatics; 757-782
Real-time kernels are often utilized to simplify the design of embedded time/safety-critical applications. However, embedded systems are sensitive to transient and other faults, each of which can lead to various errors at various system levels and ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=issn13359150::678038b0d9c6c998f44a4f91944d4da0
http://www.cai.sk/ojs/index.php/cai/article/view/852
http://www.cai.sk/ojs/index.php/cai/article/view/852
Autor:
Josef Strnadel
Publikováno v:
IFAC Proceedings Volumes. 36:213-218
The existence of loops in a circuit structure causes problems in both test generation and application. Thus, the problem of identifying loops becomes an important task during testability analysis or, later, e.g., during allocation-for testability pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8bf59f5080163c63da1347a407b46a86
https://doi.org/10.1016/s1474-6670(17)33743-6
https://doi.org/10.1016/s1474-6670(17)33743-6