Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Josef S. Watts"'
Autor:
Chenming Hu, Michael Harter, Sayeef Salahuddin, Josef S. Watts, Harshit Agarwal, Yen-Kai Lin, Angada B. Sachid, Yogesh Singh Chauhan, Pragya Kushwaha, Huan-Lin Chang, Sourabh Khandelwal, Juan Pablo Duarte
Publikováno v:
IEEE Transactions on Electron Devices. 65:463-469
Anomalous transconductance with nonmono- tonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the
Autor:
Abdellatif Bellaouar, Shuming Li, K. Sundaram, Jen Shuang Wong, X. Zhang, Josef S. Watts, Jagar Singh, Jerome Ciavatti, Srikanth Samavedam, Abhijit Bandyopadhyay, Jae Gon Lee
Publikováno v:
IEEE Transactions on Electron Devices. 65:31-37
This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a ${F}_{t}/{F}_{\text {max}}$ of 314/180 GHz and 285/14
Autor:
Josef S. Watts, Mckay Thomas G
Real manufacturing processes for advanced nodes always create devices with nonideal behaviors and variations both random and systematic. We describe how the model can be used to capture systematic variation that caused differences in the layout of th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67ae74d8dea5b43c21384a0ce737fb80
https://doi.org/10.1016/b978-0-08-102401-0.00012-1
https://doi.org/10.1016/b978-0-08-102401-0.00012-1
Autor:
Chenming Hu, Josef S. Watts, Harshit Agarwal, Yogesh Singh Chauhan, Mckay Thomas G, Pragya Kushwaha, Sourabh Khandelwal, Juan Pablo Duarte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e420bf84b535b134c3c6b4ef9af753e
https://doi.org/10.1016/c2017-0-00467-6
https://doi.org/10.1016/c2017-0-00467-6
Autor:
Christoph Schwan, Andreas Huschka, Edward J. Nowak, Laegu Kang, Rick Carter, David L. Harame, Mckay Thomas G, R. Taylor, Thomas Feudel, Kok Wai Johnny Chew, Jon Kluth, Josef S. Watts, Thorsten Kammler, Juergen Faul
Publikováno v:
ECS Transactions. 75:21-27
We report RF Characteristics in a Low Power High Performance Ultra-thin Body and Box (UTBB) FDSOI technology. The technology features Si-Channel nFETs and SiGe-Channel pFETS, a gate first HiKMG stack with a gate length (LG) of 20nm, BOX thickness (TB
Autor:
K.K.S. Tan, A. Divay, S. Morvan, L.H.K. Chan, Madabusi Govindarajan, M. T. Lau, R. Taylor, Kumaran Sundaram, Kok Wai Johnny Chew, Chi Zhang, Christoph Schwan, Andreas Huschka, Yogadissen Andee, M. Hauschildt, B. Rice, Jen Shuang Wong, Josef S. Watts, A. Bcllaouar, A. Pakfar, W. LOo, C.K. Lim, Christian Schippel, Steffen Lehmann, Zhixing Zhao, S.N. Ong, S. Embabi, David Harame, W.H. Chow, J. Mazurier, Carsten Grass, G. Workman
Publikováno v:
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
This paper describes a 22nm FDSOI technology optimized for RF/mmWave applications. The offering consists of high speed mmWave FET transistors, and a thick dual copper back-end. The offering is integrated with a low power digital technology (0.4V) and
Autor:
Kok Wai Johnny Chew, Lye Hock Chan, L. Pirro, El Mehdi Bazizi, R. Taylor, Yogadissen Andee, Josef S. Watts, Christoph Schwan, Edward J. Nowak, Thomas Feudel, Thorsten Kammler, Steffen Lehmann, S.N. Ong, Bryan Rice, Elke Erben, W.H. Chow, Elliot John Smith, J. Mazurier, David Harame, Kumaran Sundaram
Publikováno v:
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
We report an experimental pFET with 420GHz f T , which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET chann
Autor:
A. Mehta, S. Mahajan, Owen Hu, Kok Wai Johnny Chew, Kumaran Sundaram, Abdellatif Bellaouar, Palanivel Balasubramaniam, Jerome Ciavatti, Ram Asra, Jung-Suk Goo, Ravi M. Todi, H. S. Yang, David Harame, Jagar Singh, Abhijit Bandyopadhyay, S. Yamaguchi, Jen Shuang Wong, C. Kyono, Josef S. Watts, Shuming Li, D. K. Sohn, X. Zhang, Shesh Mani Pandey, E. Geiss, Srikanth Samavedam, Alexander L. Martin, AJ Bousquet, S. B. Mittal, Baofu Zhu
Publikováno v:
2017 Symposium on VLSI Technology.
This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent F t /F max of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET R
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31:1920-1924
A technique for extracting statistical compact model parameters using artificial neural networks (ANNs) is proposed. ANNs can model a much higher degree of nonlinearity compared to existing quadratic polynomial models and, hence, can even be used in
Autor:
Xi Sung Loo, Josef S. Watts, Bhoopendra Singh, Uwe Kahler, Michael Cheng, Murali Kota, S.N. Ong, Ralf Illgen, Maciej Wiatr, Byounghak Lee, Christoph Schwan, Oscar D. Restrepo, Kok Wai Johnny Chew, W.H. Chow, Andreas Huschka
Publikováno v:
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
We report experimental improvement of both RF and digital AC performance of a 28nm CMOS technology by predoping the gate poly. The results are explained in terms of the physical structure of the gate and the atomic structure of the gate TiN/Si interf