Simulation-Based Evaluation Strategy for Task Mapping Approaches in WNoC Platforms

Autor: José Edinson Aedo Cobo, Nader Bagherzadeh, Luis German Garcia Morales

Publikováno v: PDP

Network-On-Chip (NoC) along with its extension Wireless NoC (WNoC) were proposed to increase system performance in future generations of Multi-Processor System-on-Chip (MPSoC) with hundreds / thousands of cores. For such platforms, designers seek to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2b6eb847533dde2068b74bed127528d7
https://doi.org/10.1109/pdp2018.2018.00104

Mechanisms to manage intellectual property in collaborative innovation projects

Autor: James Alberto Morales Chincha, María del Socorro López Gómez, José Edinson Aedo-Cobo

Publikováno v: Revista Internacional de Organizaciones = International Journal of Organizations; Núm. 16 (2016); p. 83-98
oai:raco.cat:article/314506
Repositori Institucional de la Universitat Rovira i Virgili
Universitat Rovira i virgili (URV)
Repositorio UdeA
Universidad de Antioquia
instacron:Universidad de Antioquia
Revista Internacional de Organizaciones, Iss 16 (2016)

This paper presents some mechanisms for managing Intellectual Property (IP) in collaborative innovation projects, especially those using co-creation techniques. The mechanisms selection was made from a documentary review that allowed to identify the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5905ea7e79b30c08345f7e90788f04e4
http://hdl.handle.net/20.500.11797/RP943

Study and Implementation of Mobile WiMAX (Worldwide Interoperability for Microwave Access) Drivers for Digital Mobile Companions

Autor: José Edinson Aedo Cobo, Henry Alberto Arcila Ramírez, Eugenio Duque Pérez

Publikováno v: Sistemas y Telemática. 8:27

The accelerated progress in the mobile industry market has attracted a growing interest in research in the field of wireless communications technologies. Today, the applications and services demand highest connection data transmission rates. The 3G a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e5020504bf1e8ea3e6a49744d60122ef
https://doi.org/10.18046/syt.v8i15.1019

Timing logic analyzer implemented in reprogrammable digital architecture

Autor: Eugenio Antonio Duque Pérez, José Édinson Aedo Cobo, Julián Correa, Alexis Alberto Ramírez Orozco, Rubén Darío Nieto Londoño, Camilo Torres, Álvaro Bernal Noreña

Publikováno v: Revista Facultad de Ingeniería Universidad de Antioquia, Iss 34 (2005)

The conception, design, simulation, and implementation of a timing logic analyzer implemented on a reprogrammable digital architecture are described in this paper. The system was specified in VHDL [1] and implemented in a platform based on a FPGA (Fi

Externí odkaz: https://doaj.org/article/a85959eda1ce43e1847ca58c8398dbb8