Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Jorge Entradas"'
Publikováno v:
2023 34th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::344e8498ab7ebd597f2af78fa8bff496
https://doi.org/10.1109/asmc57536.2023.10121075
https://doi.org/10.1109/asmc57536.2023.10121075
Autor:
Thuy Do, J-C. Le Denmat, John L. Sturtevant, Jorge Entradas, Elodie Sungauer, Emek Yesilada, J-C. Michel, Yuri Granik, Frederic Robert, A-M. Armeanu
Publikováno v:
SPIE Proceedings.
Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18ec1e1e38104c79bbb2bf2893918942
https://doi.org/10.1117/12.2027291
https://doi.org/10.1117/12.2027291
Autor:
Emek Yesilada, Thuy Do, Jean-Christophe Michel, Frederic Robert, John L. Sturtevant, Jean-Christophe Le Denmat, Jorge Entradas, Yuri Granik, Elodie Sungauer, Ana-Maria Armeanu
Publikováno v:
SPIE Proceedings.
Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist [1]. This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technolo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f09a96fd0bc8d1214a2601f9e2acd5ff
https://doi.org/10.1117/12.2011412
https://doi.org/10.1117/12.2011412
Publikováno v:
SPIE Proceedings.
Resolution Enhancement Techniques have continuously improved over the last decade, driven by the ever growing constraints of lithography process. Despite the large number of RET applied, some hotspot configurations remain challenging for advanced nod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9c14ea5ac19ae05ea158a46cefaca03
https://doi.org/10.1117/12.2010111
https://doi.org/10.1117/12.2010111
Autor:
Clement Moyroud, Alexandre Villaret, S. Postnikov, J. N. Pena, Vincent Farys, Charlotte Beylier, F. Bernard Granger, Olivier Toublan, Jorge Entradas, Frederic Robert, F. Chaoui, C. Gardin, Ana-Maria Armeanu, Emek Yesilada
Publikováno v:
SPIE Proceedings.
The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival of EUV tools. New
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e00154aa1cce6b42548a7049349f41a
https://doi.org/10.1117/12.915825
https://doi.org/10.1117/12.915825
Publikováno v:
SPIE Proceedings.
At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient lev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e65840d5ab39c508cff45a3e3843a55
https://doi.org/10.1117/12.829894
https://doi.org/10.1117/12.829894
Autor:
Corinne Miramond, Kevin Lucas, Kyle Patterson, Olivier Toublan, Yorick Trouiller, Jorge Entradas, Robert Boone, Jerome Belledent, Amandine Borjon
Publikováno v:
SPIE Proceedings.
In the last 2 years, the semiconductor industry has recognized the critical importance of verification for optical proximity correction (OPC) and reticle/resolution enhancement technology (RET). Consequently, RET verification usage has increased and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::110acccfed08a76be4e65c7570a07aea
https://doi.org/10.1117/12.658823
https://doi.org/10.1117/12.658823
Autor:
Amandine Borjon, Thierry Devoivre, Jerome Belledent, Yorick Trouiller, Yves Rody, Jean-Damien Chapon, Jorge Entradas, Jean-Christophe Urbani, Franck Foussadier, Stanislas Baron, Kevin Lucas, Frank Sundermann, Christophe Couderc, Kyle Patterson, Franck Arnaud
Publikováno v:
Design and Process Integration for Microelectronic Manufacturing III.
In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following seque
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f9004d7536c73bd81075408b69e62a3
https://doi.org/10.1117/12.600887
https://doi.org/10.1117/12.600887