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pro vyhledávání: '"Jorg Radecker"'
Autor:
Matthias Goldbach, B. Uhlig, Erhard Landgraf, G. Ilicali, M. Stadele, Jorg Radecker, J. Lindolf, S. Finsterbusch
Publikováno v:
2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
Based on a detailed I-V analysis, 2D/3D process/device simulation, and inline wafer bow measurements, we have investigated a number of stress-induced layout effects on MOSFET performance caused by hybrid STI fills (HARP/HDP and SOG/HDP). Variations o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14f62e74d1db92ae961d09b1d08f512c
https://doi.org/10.1109/vtsa.2008.4530831
https://doi.org/10.1109/vtsa.2008.4530831
