Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Jooho Wang"'
Publikováno v:
IEEE Access, Vol 10, Pp 11382-11403 (2022)
In this paper, a new pre-RTL simulator is proposed to predict the power, performance, and area of convolutional neural network (CNN) dataflows prior to register-transfer-level (RTL) design. In the simulator, a novel approach is adopted to implement a
Externí odkaz:
https://doaj.org/article/c81ac3dfbd8948d4a95c5cd7e734a0e1
Publikováno v:
IEEE Access, Vol 10, Pp 25901-25921 (2022)
A system simulator is proposed and developed, which can help to optimize design parameters and hence minimize the number of collisions. In order to search the optimal design parameter combination which meets the user requirement, the proposed simulat
Externí odkaz:
https://doaj.org/article/52a912e8733543f9828d51d9f2b90263
Publikováno v:
IEEE Access, Vol 9, Pp 139228-139247 (2021)
The hardware accelerator controlled by direct memory access (DMA) is greatly influenced by the communication bandwidth from/to DRAM through on-chip buses. This paper proposes a novel performance estimation algorithm to optimize the communication sche
Externí odkaz:
https://doaj.org/article/000826b2d60a4f9cb8ac3ea7a21e497f
Publikováno v:
ISOCC
A novel latency-insensitive controller architecture is proposed for a convolutional neural network (CNN) accelerator. It is shown that the proposed architecture not only guarantees the correct operation, regardless of memory latency, but also maximiz
Publikováno v:
AICAS
Sparse CNN (SCNN) accelerators tend to suffer from the bus contention of its scatter network. This paper considers the optimizations of the scatter network. Several network topologies and arbitration algorithms are evaluated in terms of performance a
Publikováno v:
AICAS
A spatial data dependence graph (S-DDG) is newly proposed to model an accelerator dataflow. The pre-RTL simulator based on the S-DDG helps to explore the design space in the early design phase. The simulation results show the impact of memory latency
Publikováno v:
Electronics
Volume 10
Issue 3
Electronics, Vol 10, Iss 231, p 231 (2021)
Volume 10
Issue 3
Electronics, Vol 10, Iss 231, p 231 (2021)
A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design
Autor:
Chaeeun Lee, Sanghun Lee, Myungwoo Oh, Jooho Wang, Sunwoo Kim, Youngho Seo, Chester Sungchung
Publikováno v:
ISOCC
Convolutional-Neural-Network (CNN) is used in broad applications. There are dataflows for convolutional layers in CNN such as row-stationary and weight-stationary. However, these dataflows have strengths and weaknesses. This paper analyzed two repres