Zobrazeno 1 - 10
of 79
pro vyhledávání: '"Jongwook Kye"'
Publikováno v:
IEEE Transactions on Electron Devices. 70:2941-2946
Autor:
Jongwook Kye
Publikováno v:
DTCO and Computational Patterning.
Autor:
Giyoung Yang, Hakchul Jung, Jinyoung Lim, Jaewoo Seo, Ingyum Kim, Jisu Yu, Hyeoungyu You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, Woojin Rim, Hayoung Kim, Dalhee Lee, Sanghoon Baek, Jonghoon Jung, Taejoong Song, Jongwook Kye
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
Hyunjin Shin, Sangkyung Won, Dohui Kim, Byunghun Choi, Gyusung Kim, Myeonghee Oh, Jaeseung Choi, Jongwook Kye
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
Woonggyu Lee, Seungjae Jung, Bonhyuck Koo, Jongwook Kye, Ahmed Saleh, Ahmed Gharieb, Mohamed Elrefaee, Mohamed Alimam
Publikováno v:
2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS).
Publikováno v:
VLSI Circuits
A 28nm embedded Flash memory in this paper is designed for the Automotive application in Foundry. Through Temperature Auto-Tracking Sense Amplifier using the Bit line Charge Boost (BCB) and Bit line Leakage current Compensation (BLC) technology, it s
Autor:
Taejoong Song, Hoyoung Tang, Jae-Seung Choi, Baeck Sang-Yeop, Lee Inhak, Dong-Wook Seo, Jongwook Kye
Publikováno v:
VLSI Circuits
Voltage Auto Tracking Cell Power Lowering (VACPL) Write Assist circuit is proposed for low-power SRAM with dual-rail architecture. VACPL adaptively controls the cell voltage with respect to the dual rail offset voltage to maximize bitcell write-abili
Autor:
Jaehong Park, Taejung Lee, Woojin Rim, Geum-Jong Bae, Hoonki Kim, Taeyeong Kim, Jong-Hoon Jung, Dong-Won Kim, S. D. Kwon, Hakchul Jung, Hyung-Tae Kim, Taejoong Song, Soon-Moon Jung, Sanghoon Baek, Keun Hwi Cho, Jongwook Kye
Publikováno v:
ISSCC
Advanced technologies help to improve SRAM performance via recent transistor breakthroughs [1], which allow SRAM designers to focus on handling metal resistance by alleviating device performance impediments. Since SRAM margins are more vulnerable to
Autor:
Manuj Rathor, Suk-Soo Pyo, Steve Ngueya Wandji, Andrew Sowden, Jean Christophe Vial, Alexandra Gourio, Gwan-Hyeob Koh, El Mehdi Boujamaa, Jongwook Kye, Samsudeen Mohamed Ali, Yoon-Jong Song, Cyrille Dray, Taejoong Song
Publikováno v:
VLSI Circuits
In this paper we present a read circuitry that tackles all STT-MRAM read challenges. First, a negative temperature coefficient (NTC) reference based on an MTJ in series with an “NTC” resistor circuit emulator is described. Then, an offset cancell
Autor:
Hyuck-Chai Jung, T.H. Choi, Hyun-Chul Kim, Jeong-Dong Choi, Seong-Ook Jung, Taejoong Song, H.W. Choi, Hyuck Choo, Jongwook Kye
Publikováno v:
2019 Symposium on VLSI Technology.
High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents $(I_{\text{d