Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Jongeun Koo"'
Publikováno v:
Frontiers in Neuroscience, Vol 12 (2018)
Spiking Neural Networks (SNNs) have high potential to process information efficiently with binary spikes and time delay information. Recently, dedicated SNN hardware accelerators with on-chip synapse memory array are gaining interest in overcoming th
Externí odkaz:
https://doaj.org/article/5d28810718c143fdaad59dc29ed4a7ef
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:2245-2255
We introduce a new clocking approach for digital systems to achieve better resilience to process, voltage, and temperature (PVT) variations. The proposed scheme is based on elastic clock methodology that uses locally generated clocks and elastic hand
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7dcaae24c94692fdf3f23be201362729
https://doi.org/10.1109/jssc.2020.3048881
https://doi.org/10.1109/jssc.2020.3048881
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 20:195-203
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e196f4ada69d6c3e20e38dc5e05744e1
https://doi.org/10.5573/jsts.2020.20.2.195
https://doi.org/10.5573/jsts.2020.20.2.195
Publikováno v:
VLSI Circuits
We introduce a SRAM-based binary neural network (BNN) hardware which uses a single 6T SRAM cell for XNOR operation for the first time. The cell is 45% smaller than the previous 8T bitcell for XNOR operation. We also propose an in-memory calibration a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::027b9e59bc2159d2ca68119dc239baab
https://doi.org/10.23919/vlsic.2019.8778160
https://doi.org/10.23919/vlsic.2019.8778160
Publikováno v:
CICC
This paper presents a 6T SRAM-based transposable synapse memory aiming to improve online learning performance of neuromorphic processors at the minimum area cost. While a custom 8T SRAM was used in the previous transposable synapse memory, the propos
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4dc3732a11cfe0112968dd8999ea6ef
https://doi.org/10.1109/cicc.2019.8780165
https://doi.org/10.1109/cicc.2019.8780165
Publikováno v:
ISLPED
The elastic clock scheme is a robust design methodology to ensure timing closure under PVT variation using locally generated clocks and handshaking protocol. However, it still has a chance of timing errors due to delay mismatch between the data-path
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1994b2924605e1465af9795feb7eaa8e
https://doi.org/10.1109/islped.2017.8009203
https://doi.org/10.1109/islped.2017.8009203
Publikováno v:
IEICE Electronics Express. 16:20190180-20190180
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::001c904bd84262eb3282396524d3d093
https://doi.org/10.1587/elex.16.20190180
https://doi.org/10.1587/elex.16.20190180
Autor:
Eunhyeok Park, Sungjoo Yoo, Jae-Joon Kim, Dongyoung Kim, Sungju Ryu, Jongeun Koo, Eun-Woo Song, Junki Park
Publikováno v:
A-SSCC
We propose a new timing error correction scheme for area-efficient design of flip-flop based pipeline. Key features in the proposed scheme are 1) one-cycle error correction using a new local stalling scheme and 2) selective replacement of the error d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7f5e984ad6a7887d1056e6aa75bea28
https://doi.org/10.1109/asscc.2016.7844154
https://doi.org/10.1109/asscc.2016.7844154
Autor:
Sooyoung Ahn, Younghoi Cheon, Jongeun Koo, Bo-Sun Hwang, Jong-bae Lee, Chanseok Hwang, Moon-Hyun Yoo
Publikováno v:
ISQED
With the increase in circuit frequency and supply voltage Scaling, a robust power network design is essential to ensure that the circuits on a chip operate reliably at the guaranteed level of performance. Traditionally the power network analysis has
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8685bf0747b24757689f529d07c5be31
https://doi.org/10.1109/isqed.2011.5770799
https://doi.org/10.1109/isqed.2011.5770799
Publikováno v:
ISQED
In the trends of high density high speed and low power consumption, the analysis of power distribution networks is rapidly becoming an essential step in the design of high performance ICs. Nevertheless, the analysis is a great challenge, due to the l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45007ec298cd8214849259a1e758149e
https://doi.org/10.1109/isqed.2004.1283664
https://doi.org/10.1109/isqed.2004.1283664