Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Jong-Mil Youn"'
Autor:
Yuri Yasuda-Masuoka, Jaehun Jeong, Kihwang Son, SeungWook Lee, Seulki Park, Youngho Lee, Ju Youn Kim, Jaeho Lee, Moongi Cho, Sihyung Lee, Soohun Hong, Heebum Hong, Younghun Jung, Changkeun Yoon, Yonghyun Ko, Kyunghoon Jung, Taehun Myung, Jong Mil Youn, Gitae Jeong
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6ed776a19715b49489ce62a2a6dafe1
https://doi.org/10.1109/iedm19574.2021.9720656
https://doi.org/10.1109/iedm19574.2021.9720656
Autor:
Won Ji Park, Jae Hee Oh, Ji Hyung Kim, Seong Wook Moon, Jeong Hoon Ahn, Ding Shaofeng, Jung Ho Park, Won Hyoung Lee, Min Guk Kang, Choi Yun Ki, Seung Ki Nam, Je Gwan Hwang, Jong Mil Youn
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
Interposer to interconnect between the electronic components has been developed for the last few decades because it can improve the system performance effectively, compared to the system with intra-chip wiring. In this paper, the integrated stack cap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::342c132f1ebe9f90373a841699094d8f
https://doi.org/10.1109/iitc51362.2021.9537342
https://doi.org/10.1109/iitc51362.2021.9537342
Autor:
Jong-Mil Youn, Kichang Sung, Ju-Heon Kim, Jeong-Hoon Ahn, Wonkyu Han, Junki Jang, Yun-Ki Choi, Woojin Jang, Hoon Kim, Chang-Hyun Kim, Hyunju Yim, Wonmo Kang, Rak-Hwan Kim, Youngju Lim, Young Soo Yoon, Dongwoo Shin
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
We demonstrate that when a thin ALD (atomic layer deposition) TaN as a barrier metal is deposited to the Cu interconnect, the upper via resistance is significantly increased. We also exhibit that the abnormal upper via resistance is consistent with t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3001ed74dd45f03dcc568d479888c889
https://doi.org/10.1109/iitc51362.2021.9537395
https://doi.org/10.1109/iitc51362.2021.9537395
Autor:
Young-Gun Ko, Jeongmin Choi, Y. Yasuda-Masuoka, Kyunghoon Jung, Heebum Hong, Sungil Jo, Jae-Hun Jeong, Minseong Lee, Young-Ho Lee, Sihyung Lee, Ju Youn Kim, Gitae Jeong, Kihwang Son, Ho Lee, Byungha Choi, Hyung-Jong Lee, Chunghwan Shin, Jong Mil Youn, Sung Won Kim, Jae-Chul Kim
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
In this paper, we demonstrate state of the art 5nm technology (5LPE) having co-optimization process for Dual CPP (Critical Poly-Pitch) technology to maximize Product Power-Performance-Area by separating both high speed and low power blocks. As a resu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0efae1aa35f1f41261d412f146b43f5
https://doi.org/10.1109/iedm13553.2020.9371958
https://doi.org/10.1109/iedm13553.2020.9371958
Autor:
Nak-Jin Son, Yongmin Park, Hwa-Sung Rhee, Sung Gun Kang, Sung-il Cho, Kyung-Hwan Yeo, Eun-Cheol Lee, Yun-Ki Choi, Jong Shik Yoon, Heebum Hong, Jeong-Hoon Ahn, Dongwoo Kim, Il-Ryong Kim, Jungtae Kim, Jong Mil Youn, Jae-Hun Jeong
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
8LPP logic platform technology supports mobile and high-performance and lower power application especially for mobile, artificial intelligence (AI), and cryptocurrency devices. 8LPP is employing the evolutionary generation of bulk FinFET FEOL and 44n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::40b1037773b5c94d6df5444162cc2a3a
https://doi.org/10.1109/vlsit.2018.8510673
https://doi.org/10.1109/vlsit.2018.8510673
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
Summary form only given. A unique 6.4 /spl mu/m/sup 2/ 6Tr. SRAM cell has been developed using an advanced CMOS technology implemented in 0.25 /spl mu/m design rule for high density and high speed applications. Very small aspect ratio of 0.63 has bee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f9079f56c48725b9298e0dc383c934b2
https://doi.org/10.1109/vlsit.1998.689202
https://doi.org/10.1109/vlsit.1998.689202
Autor:
Hyun-Geun Byun, Hoon Lim, Bonghyun Choi, Ki-Joon Kim, Tae-Hong Ha, Ho-Jin Kim, Seung-jae Lee, Jin-Ho Kim, Kyeong-Tae Kim, Jong-Mil Youn
Publikováno v:
2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).
The reliability of dual gate oxide has been investigated in terms of dual gate oxide and shallow trench isolation (STI) process parameters. The thick oxide constructed by the dual gate oxide process shows intrinsic inferior quality to single-step gro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20e3959e83ba7de0a9150974ca3978c6
https://doi.org/10.1109/relphy.2001.922880
https://doi.org/10.1109/relphy.2001.922880
Publikováno v:
Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd5cb0e57e55643856d1db7db8c30f1c
https://doi.org/10.7567/ssdm.2000.a-4-3
https://doi.org/10.7567/ssdm.2000.a-4-3