Zobrazeno 1 - 10
of 85
pro vyhledávání: '"Jong-Kee Kwon"'
Autor:
Christopher M. Thomas, Young-Sub Yuk, Gyu-Hyeong Cho, Chang-Seok Chae, Yi-Gyeong Kim, Gert Cauwenberghs, Jong-Kee Kwon, Chul Kim, Sohmyung Ha
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:1653-1665
The parallel combination of a switching and a linear amplifier in the supply modulator for RF power amplifiers (PAs) has the potential to enhance energy efficiency while achieving wider bandwidth and lower ripple output voltage. In this paper, a line
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a14e3a658c706a139dc799f70b98b98
https://doi.org/10.1109/jssc.2018.2804043
https://doi.org/10.1109/jssc.2018.2804043
Autor:
Jong-Kee Kwon, Tae Moon Roh, Woo Seok Yang, Young-Deuk Jeon, Jaewoo Lee, Chun-Gi Lyuh, Yi-Gyeong Kim, Min-hyung Cho
Publikováno v:
ETRI Journal. 38:235-243
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6528926e276d8bd8eb344acc17169888
https://doi.org/10.4218/etrij.16.2515.0015
https://doi.org/10.4218/etrij.16.2515.0015
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 59:741-745
This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adop
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::223addd3fb8059318967da6718fe71ee
https://doi.org/10.1109/tcsii.2012.2222837
https://doi.org/10.1109/tcsii.2012.2222837
Publikováno v:
ETRI Journal. 34:518-526
This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::994c199f6dd0e81e310e4e18348383a9
https://doi.org/10.4218/etrij.12.0111.0417
https://doi.org/10.4218/etrij.12.0111.0417
Publikováno v:
Electronics Letters. 53:930-931
An electrical resistivity evaluation method for a pillar-shaped solid material, especially a brittle thermoelectric Bi2Te3, is presented with short compensation based on a probing apparatus with four-spring pins. The method eliminates the process of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3deefbc5eaad8b473db972b55ceaa052
https://doi.org/10.1049/el.2017.1508
https://doi.org/10.1049/el.2017.1508
Publikováno v:
ETRI Journal. 33:897-903
A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital-toanalog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29bf71dd07c9e7c2d698a95ef0237adf
https://doi.org/10.4218/etrij.11.0111.0293
https://doi.org/10.4218/etrij.11.0111.0293
Publikováno v:
Microelectronics Journal. 42:1225-1230
This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66de67e497650a696990a426ec9e0d0d
https://doi.org/10.1016/j.mejo.2011.08.002
https://doi.org/10.1016/j.mejo.2011.08.002
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:1881-1892
A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a014b00c89671141ee2a5fcd73b9b1cb
https://doi.org/10.1109/jssc.2011.2151450
https://doi.org/10.1109/jssc.2011.2151450
Autor:
Yi-Gi Kwon, Younglok Kim, Min-Ho Choi, Jong-Kee Kwon, Seung-Hoon Lee, Hyelim Park, Young-Deuk Jeon
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 11:95-103
This paper proposes a 6b 1.2 GS/s 47.8 ㎽ 0.17 ㎟ 65 ㎚ CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 V p-p at a 1.2 V supply voltag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::364130b98e6f2287b6cb5b89202cc6a4
https://doi.org/10.5573/jsts.2011.11.2.095
https://doi.org/10.5573/jsts.2011.11.2.095
Publikováno v:
IEEE Sensors Journal. 11:1134-1144
We present a low-power, low complexity, and wide-dynamic-range universal sensor readout circuit that converts the sensing capacitance or resistance changes to digital duty cycles based on pulsewidth modulation (PWM). The readout circuit utilizes a RC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74ef696c2602e79c1ade4b7e57dbbfe8
https://doi.org/10.1109/jsen.2010.2085430
https://doi.org/10.1109/jsen.2010.2085430