Zobrazeno 1 - 10
of 62
pro vyhledávání: '"Jong-Kai Lin"'
Publikováno v:
Microelectronics Reliability. 61:64-70
Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realiz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ada98d2920972fd3cb4a902835b2229d
https://doi.org/10.1016/j.microrel.2015.12.041
https://doi.org/10.1016/j.microrel.2015.12.041
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 5:1273-1283
Cu pillar technology can cater for high I/O, fine pitch, and miniaturization requirements compared with wire bonding and conventional solder flip-chip technologies. However, chip–package interaction of Cu pillar and low- $k$ chip is a critical chal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e779a6cd835ae0de0566237edd6e3791
https://doi.org/10.1109/tcpmt.2015.2461020
https://doi.org/10.1109/tcpmt.2015.2461020
Autor:
Roshan Weerasekera, Surya Bhattacharya, Songbai Zhang, Soon Wee Ho, Jong-Kai Lin, Li Hong Yu, Guruprasad Katti, Rahul Dutta, Ka Fai Chang, Srinivasa Rao Vempati
Publikováno v:
IEEE Design & Test. 32:23-31
A through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration is reviewed. Polymer-based Cu-RDL interconnects provide a CM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7a450201e70f601337d3d23e2867568
https://doi.org/10.1109/mdat.2015.2424429
https://doi.org/10.1109/mdat.2015.2424429
Publikováno v:
Journal of Applied Physics; 6/15/2004, Vol. 95 Issue 12, p8286-8289, 4p, 3 Black and White Photographs, 2 Diagrams
Autor:
Jong-Kai Lin, Fa Xing Che, Sharon Pei Siang Lim, Hsiang-Yao Hsiao, Alvin Chow, Jie Li Aw, K. Y. Au, Xiaowu Zhang
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
This paper reports on the development of packaging technology for the assembly of 30µm pitch micro Cu pillar bump (15µm diameter) on organic FCCSP substrate having bare Cu bondpad without NiAu or OSP surface protection. The assembly was performed b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2772ee0ae849cebaaa42fd30515ba9d4
https://doi.org/10.1109/ectc.2016.127
https://doi.org/10.1109/ectc.2016.127
Publikováno v:
Journal of Materials Research. 22:826-830
Void formation in lead-free solder joints, away from the joint interface, has been observed after solid-state aging. These voids are attached to intermetallic precipitates in the solder matrix, especially to those that are adjacent to the layered int
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fe8d88e7ac8da238a853880805fd2af
https://doi.org/10.1557/jmr.2007.0131
https://doi.org/10.1557/jmr.2007.0131
Publikováno v:
IEEE Transactions on Electronics Packaging Manufacturing. 30:49-53
High strain-rate drop impact tests were performed on ball grid array (BGA) packages with solder compositions of (in wt%) Sn-3.8Ag-0.7Cu (SnAgCu) and eutectic Sn-37Pb (SnPb). Solder balls were joined to the metallizations of plated Ni on the device si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ead8179f29589613680f301343939988
https://doi.org/10.1109/tepm.2006.890643
https://doi.org/10.1109/tepm.2006.890643
Autor:
Jong-Kai Lin, Hsiang-Yao Hsiao
Publikováno v:
2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).
Current-induced failures in fine pitch Sn micro-bump with Cu pillar have been investigated under a high current density of 3∗105 A/cm2 and temperature of 150°C. Both joule heating and high current density led to void formation and an abrupt increa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cd4e513657020062487e5f2a88d6a59
https://doi.org/10.1109/eptc.2015.7412351
https://doi.org/10.1109/eptc.2015.7412351
Publikováno v:
2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).
In flip chip technology, flux is widely used to clean the surface of the solder bumps and the surfaces to be soldered for good wetting of the solder bumps on the conductive bond pads [1]. Moreover, flux helps to keep the flipped chip in position and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c14be8c73e117b5f265d64f366691cf8
https://doi.org/10.1109/eptc.2015.7412342
https://doi.org/10.1109/eptc.2015.7412342
Publikováno v:
2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).
A compliant flip chip bump design compromises of a polymer core inside a Cu pillar, a polymer encapsulated Cu pillar and the process flow to make such bumps for fine pitch flip chip package is proposed in this study. Both polymer core and polymer enc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ed314d56b1e6d72c397c89bf24e1345
https://doi.org/10.1109/eptc.2015.7412352
https://doi.org/10.1109/eptc.2015.7412352