Výsledky vyhledávání - "Jong Shik Yoon"

High-speed and Ultra-low Power IoT One-chip (MCU + Connectivity-chip) on a Robust 28-nm Embedded Flash Process

Publikováno v: 2019 Symposium on VLSI Technology.

Based on robust 28-nm embedded flash (eFlash) process, IoT One-chip for high-speed and low power applications which MCU-chip (10Mb eFlash) and connectivity-chip (BLE/Zigbee) are integrated for the first time. By introducing new devices on 28-nm low-p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::df4bf7035e94dc151fda06691cac7370
https://doi.org/10.23919/vlsit.2019.8776557

Zobrazit plný text záznamu

Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT Application

Publikováno v: 2018 IEEE Symposium on VLSI Technology.

We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (−40~125°C) with >1E+6 endurance and >10 year retention for high speed MCU/IoT application. Robust cell operation is also demonstrated after

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0f4b5a2ce996887b82fc42cbf625362c
https://doi.org/10.1109/vlsit.2018.8510623

Zobrazit plný text záznamu

Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications

Autor: Y.S. Bang, S. D. Kwon, Jung-Chak Ahn, Taejoong Song, Jaesuk Jung, J. H. Do, Y. Yasuda-Masuoka, Yun-Kyoung Lee, Byungha Choi, Hoonki Kim, Jong Shik Yoon, Y.D. Lim, Kyu-Charn Park

Publikováno v: 2018 IEEE Symposium on VLSI Technology.

11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performan

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6e4d8a167499f74977faa83ff33e6c12
https://doi.org/10.1109/vlsit.2018.8510694

Zobrazit plný text záznamu

8LPP Logic Platform Technology for Cost-Effective High Volume Manufacturing

Autor: Nak-Jin Son, Yongmin Park, Hwa-Sung Rhee, Sung Gun Kang, Sung-il Cho, Kyung-Hwan Yeo, Eun-Cheol Lee, Yun-Ki Choi, Jong Shik Yoon, Heebum Hong, Jeong-Hoon Ahn, Dongwoo Kim, Il-Ryong Kim, Jungtae Kim, Jong Mil Youn, Jae-Hun Jeong

Publikováno v: 2018 IEEE Symposium on VLSI Technology.

8LPP logic platform technology supports mobile and high-performance and lower power application especially for mobile, artificial intelligence (AI), and cryptocurrency devices. 8LPP is employing the evolutionary generation of bulk FinFET FEOL and 44n

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::40b1037773b5c94d6df5444162cc2a3a
https://doi.org/10.1109/vlsit.2018.8510673

Zobrazit plný text záznamu

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications

Autor: Changnam Park, Jae-Seung Choi, Woojin Rim, Yongho Kim, Sunghyun Park, Hyun-Taek Jung, Bongjae Kwon, Jong-Hoon Jung, Jeongho Do, Sungwee Cho, Hyun-su Choi, Jong Shik Yoon, Taejoong Song, Hoonki Kim

Publikováno v: ISSCC

SRAM plays an integral role in the power, performance, and area of a mobile system-on-a-chip. To achieve low power and high density, extreme ultraviolet (EUV) technology is adopted for the 7nm FinFET technology [3-4]. Conventional ArF immersion with

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0b353f20952db8bf5c5ec23baf6eb0c6
https://doi.org/10.1109/isscc.2018.8310252

Zobrazit plný text záznamu

A 14 nm FinFET 128 Mb SRAM With V $_{\rm MIN}$ Enhancement Techniques for Low-Power Applications

Publikováno v: IEEE Journal of Solid-State Circuits. 50:158-169

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 $\mu$ m $^{2}$ and a 0.080 $\mu$ m $^{2}$ 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve ${\rm V}_{{\

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::aff5fc60370a6af25017b3dd3a8da8a7
https://doi.org/10.1109/jssc.2014.2362842

Zobrazit plný text záznamu

10nm 2nd generation BEOL technology with optimized illumination and LELELELE

Publikováno v: 2017 Symposium on VLSI Technology.

10nm 2nd generation BEOL technology is described with an optimized illumination system and multi-patterning lithography. While the optimized illumination system offered a possibility to pattern reduced metal pitches in the preferred orientation, diff

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::018cd547c8f07b2981b2a159d22ddf67
https://doi.org/10.23919/vlsit.2017.7998156

Zobrazit plný text záznamu

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Autor: Joo-Hyun Jeong, Hansu Oh, Kang-Wook Park, Jedon Kim, Jaehoon Park, Jin Hyoun Joe, Jinsung Lim, Han-Su Kim, Jong Shik Yoon, Chulho Chung

Publikováno v: IEEE Transactions on Electron Devices. 55:2712-2717

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly Cgb, beco

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c71c290fc9f4211d09e419442e317f98
https://doi.org/10.1109/ted.2008.2003995

Zobrazit plný text záznamu

Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell

Publikováno v: 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning proc

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fd261df88649d6b28565d096db8e59f3
https://doi.org/10.1109/vlsit.2014.6894366

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání