Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Jonathan P Lotz"'
Autor:
Neela B. Gaddis, Jonathan P Lotz
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1697-1702
The HP-PA8000 is a 180-MHz quad-issue custom VLSI implementation of the HP-PA 2.0 64-b architecture delivering 11.84 SPECint95 and 20.18 SPECfp95 with 3.8 million transistors integrated on a 17.68 mm/spl times/19.1 mm die in a 3.3-V, 0.5-/spl mu/m CM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b6512fd0530e949505a229e08dfad43
https://doi.org/10.1109/jssc.1996.542314
https://doi.org/10.1109/jssc.1996.542314
Autor:
Shekhar Borkar, Jonathan P. Lotz, Ty Garibay, Ruchir Puri, Robert K. Montoye, William H Joyner
Publikováno v:
DAC
Due to ever increasing cost of doing design, design productivity and more specifically, cost of design has become a major bottleneck in large scale design projects. Due to the cost crunch, automated synthesis techniques have been gaining ground on ma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84ebfe17b37807d49c6fc5a5a55e8abb
https://doi.org/10.1145/1391469.1391719
https://doi.org/10.1145/1391469.1391719
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:1190-1198
A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAMs. Key performa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e2292826aad76078fd5f169327de10c
https://doi.org/10.1109/4.62141
https://doi.org/10.1109/4.62141
Autor:
Michael A Buckley, Craig A. Gleason, D. Hollenbeck, Richard J. Luebs, K. Erskine, Joel D. Lamb, B. Long, J. Wheeler, S. McMullen, J. Yetter, C. Kohlhardt, H. Hill, Daniel L Halperin, Jonathan P Lotz, Robert J. Horning, Patrick Knebel, R. Novak, Darius Tanksalvala, H. Tran, L. Sigel, C. Simpson, Doug Quarnstrom, Donald Kipp, John R. Spencer, S. Chapin, Eric Delano, Duncan Weir, E. Rashid, Thomas R. Hotchkiss, M. Forsyth, T. Gaddis
Publikováno v:
1990 37th IEEE International Conference on Solid-State Circuits.
A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both comme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a72489e0852fc0c8239643d7019fe6b
https://doi.org/10.1109/isscc.1990.110125
https://doi.org/10.1109/isscc.1990.110125
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