Výsledky vyhledávání - "Jon D. Cheek"

Sub-50nm gate length SOI transistor development for high performance microprocessors

Publikováno v: Materials Science and Engineering: B. :3-8

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::abb84ee304cfa2679774d71a12b2b9b9
https://doi.org/10.1016/j.mseb.2004.07.077

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Characteristic Study of SOI eSiGe Techonology

Autor: R. Noble, J. Hildreth, S. Venkatesan, C.C. Fu, Mark D. Hall, V. Dhandapani, Venkat R. Kolagunta, D. Eades, Bich-Yen Nguyen, Hunter J. Martinez, Laegu Kang, Da Zhang, T. Kropewnicki, Jon D. Cheek, Darren V. Goedeke, M. Jahanbani, A. Nagy

Publikováno v: 2007 IEEE International SOI Conference.

This paper presents a detailed study of SOI source/drain embedded SiGe (eSiGe) technology with a focus on parasitic characteristics. It shows that eSiGe can appreciably suppress on-state floating body effect and improve device exterior resistance. Al

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::585f475f80832b54559a0cdbd6657df7
https://doi.org/10.1109/soi.2007.4357833

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High Performance NMOS Transistors for 45nm SOI Technologies

Autor: Venkat R. Kolagunta, Laegu Kang, Jon D. Cheek, Gregory S. Spencer, Stefan Zollner, Xiang-Zheng Bo, Kurt H. Junker, Tien Ying Luo

Publikováno v: 2007 IEEE International SOI Conference.

We demonstrate NMOS performance enhancements of up to ~18% for applications in a 45 nm SOI technology. The performance boost was achieved using high tensile-stressed UV film in conjunction with stress memorization techniques (SMT). For the first time

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6625915328f5197b0f92b8d678dfbb8f
https://doi.org/10.1109/soi.2007.4357830

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High performance, highly reliable FD/SOI I/O MOSFETs in contemporary high-performance PD/SOI CMOS

Autor: Brian A. Winstead, Vishal P. Trivedi, A. Haggag, S. Parsons, M. Moosa, Hector Sanchez, Tien Ying Luo, Laegu Kang, Venkat R. Kolagunta, Jon D. Cheek, P. Choi, M. Khazhinsky

Publikováno v: 2007 IEEE International SOI Conference.

Integration of fully-depleted SOI (FD/SOI) MOSFETs for high performance 3.3 V/2.5 V I/O applications in contemporary high-performance partially-depleted SOI (PD/SOI) CMOS is reported for the first time. The FD/SOI MOSFETs feature dual etch-stop layer

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8cf40bfe0d4e675f695008b9610d0607
https://doi.org/10.1109/soi.2007.4357863

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Uniaxial and Biaxial Strain for CMOS Performance Enhancement

Publikováno v: Scopus-Elsevier

Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a4374c45132a6872abaa958490fd0c29
https://doi.org/10.1109/istdm.2006.1716039

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1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

Autor: M. Jahanbani, Jon D. Cheek, N. Cave, S.j. Lian, Konstantin V. Loiko, Mehul D. Shroff, Chi-Hsi Wu, Stanley M. Filipiak, Xiang-Zheng Bo, H.C. Tuan, M. Azrak, Paul A. Grudowski, Wen-Jya Liang, Vance H. Adams, Sinan Goktepeli, Venkat R. Kolagunta, M. Foisy, John J. Hackenberg

Publikováno v: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit desig

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::33649abd039e0c65218d78c61cea5101
https://doi.org/10.1109/vlsit.2006.1705217

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Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS

Autor: Gregory S. Spencer, P. Choi, J. Liu, D. Sing, Venkat R. Kolagunta, Jon D. Cheek, Vishal P. Trivedi, Paul A. Grudowski, S. Parsons

Publikováno v: 2006 IEEE international SOI Conferencee Proceedings.

Extrinsic source/drain series resistance (RSD/) becomes a limiting factor as performance boosters, such as strain-Si and metal-gate/high-k gate stack that enhance the intrinsic MOSFET, are vigorously pursued and implemented in nanoscale CMOS (Ghani,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e7eebbd09591fc5c4d45b0fda1da73c3
https://doi.org/10.1109/soi.2006.284412

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Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations

Autor: Qianghua Xie, L. Prabhu, Y.C. Sun, J. Mogab, Bich-Yen Nguyen, H.C. Tuan, Jon D. Cheek, S. Venkatesan, S. Murphy, Mong-Song Liang, C.H. Chang, Ted R. White, Yuan-Hung Chiu, Victor H. Vartanian, Aaron Thean, Y.C. See, M. Ramon, H. Collard

Publikováno v: IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

This paper describes the novel stress engineering of SC-SSOI devices through the interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation. We have demonstrated a method of uniaxial stress rela

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https://doi.org/10.1109/iedm.2005.1609393

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