Zobrazeno 1 - 10
of 56
pro vyhledávání: '"John Wickerson"'
Publikováno v:
Proceedings of the ACM on Programming Languages. 7:1740-1769
We describe our experiences successfully applying lightweight formal methods to substantially improve and reformulate an important part of Standard Portable Intermediate Representation SPIRV, an industry-standard language for GPU computing. The forma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a75bfea126a04ba9349a7b04ef5a94eb
https://doi.org/10.1145/3571253
https://doi.org/10.1145/3571253
Autor:
John Wickerson, Jianyi Cheng, George A. Constantinides, Jason H. Anderson, Shane T. Fleming, Yu Ting Chen
Publikováno v:
IEEE Transactions on Computers. 71:933-946
High-level synthesis (HLS) is an increasingly popular method for generating hardware from a description written in a software language like C/C++. Traditionally, HLS tools have operated on sequential code, however in recent years there has been a dri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::96c0ed280aae91b5d79b082a6fcc435d
https://doi.org/10.1109/tc.2021.3066466
https://doi.org/10.1109/tc.2021.3066466
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:628-641
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emerg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::17e87bd7755811ce033d68ee6b6b4f29
https://doi.org/10.1109/tcad.2021.3065902
https://doi.org/10.1109/tcad.2021.3065902
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:614-627
A well-known approach for generating custom hardware with high throughput and low resource usage is modulo scheduling, in which the number of clock cycles between successive inputs (the initiation interval, II) can be lower than the latency of the co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::59028d7356edf250f3e68216d6313243
https://doi.org/10.1109/tcad.2021.3060320
https://doi.org/10.1109/tcad.2021.3060320
Publikováno v:
International Conference on Field Programmable Logic and Applications
A recent theme in HLS research is the production of dynamically scheduled circuits, which are made up of components that use handshaking to schedule themselves at run time, as opposed to following a schedule determined statically at compile time. Dyn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::900156b9ff1f7f85ed0c6826a96e7c04
http://hdl.handle.net/10044/1/98599
http://hdl.handle.net/10044/1/98599
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:24-37
When mapping C programs to hardware, high-level synthesis (HLS) tools reorder independent instructions, aiming to obtain a schedule that requires as few clock cycles as possible. However, when synthesizing multithreaded C programs, reordering opportu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9c12b6336e0cc050968ca479e1f33598
https://doi.org/10.1109/tvlsi.2020.3026112
https://doi.org/10.1109/tvlsi.2020.3026112
Publikováno v:
2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a61087f912a6c145fca78b0e516cdbb
https://doi.org/10.1109/fccm53951.2022.9786208
https://doi.org/10.1109/fccm53951.2022.9786208
Publikováno v:
Software Testing, Verification and Reliability. 32
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::930c9779a35b396162a9bc7908ebcf03
https://doi.org/10.1002/stvr.1812
https://doi.org/10.1002/stvr.1812
Publikováno v:
IEEE International Symposium on Field-Programmable Custom Computing Machines
In high-level synthesis (HLS), loop pipelining allows multiple iterations of a loop to be executed concurrently. The start time of the operations in each iteration can be determined either at compile time (static pipelining) or at run time (dynamic p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d257643b67a9a4c518650ba11ed64c04
http://hdl.handle.net/10044/1/96646
http://hdl.handle.net/10044/1/96646
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:516-529
Many algorithms feature an iterative loop that converges to the result of interest. The numerical operations in such algorithms are generally implemented using finite-precision arithmetic, either fixed- or floating-point, most of which operate least-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d47e7b85b1283ebe381462b653374009
https://doi.org/10.1109/tvlsi.2019.2945257
https://doi.org/10.1109/tvlsi.2019.2945257