Zobrazeno 1 - 10
of 11
pro vyhledávání: '"John Taddei"'
Autor:
Joel A. Bahena, Phillip Tyler, John Taddei, Muthumanickam Sankarapandian, Jamie Prudhomme, Karthikeyan Pillai, Abdullahi Said, Christopher Carr, Dario Goldfarb, Chris Waskiewicz, Qianwen Chen
Publikováno v:
IMAPSource Proceedings. 2022
With the emergence of 3D integration and wafer level packaging, the pillar bumping process has become a critical processing step. As the process has matured, significant efforts have been made for optimization in terms of both production and cost. Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0b3774402731c8a85f792b6ca62e626
https://doi.org/10.4071/001c.74626
https://doi.org/10.4071/001c.74626
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2017:1-26
Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e51aa1b05011ac63898bf96353f34c4
https://doi.org/10.4071/2017dpc-wp2_presentation1
https://doi.org/10.4071/2017dpc-wp2_presentation1
Publikováno v:
International Symposium on Microelectronics. 2016:000463-000468
A wet silicon etch chemistry and a process using the chemistry as a simple and cost-effective alternative to the polish/plasma etch silicon thinning process are presented in this paper. The new etch chemistry improves the Si etch rate over traditiona
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1119e5d39e0b2cdd3689ee6b1d65ef1
https://doi.org/10.4071/isom-2016-tha41
https://doi.org/10.4071/isom-2016-tha41
Autor:
Mike Phenis, Richie Peters, Kimberly Dona Pollard, Ramey Youssef, Meng Guo, John Taddei, John Clark, Laura Mauer
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2014:001435-001469
The continuing challenge to meet the need for lighter, smaller, faster and smarter electronic systems has pushed the advancement of 2.5D and 3D technology. The ability to create and integrate through-silicon vias (TSV) into device designs in 2.5- and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9b03d552cc2223b8e281ebe6b6017d3
https://doi.org/10.4071/2014dpc-wp12
https://doi.org/10.4071/2014dpc-wp12
Autor:
John Clark, John Taddei, Michael Hatzistergos, Kenji Nulman, Laura Mauer, Stephen Olson, Victor Vartanian
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
Deep Reactive Ion Etch (DRIE) processes used to form Through Silicon Vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including diele
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6343adc4a500aaa83fb5423fad26f558
https://doi.org/10.1109/ectc.2016.383
https://doi.org/10.1109/ectc.2016.383
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2012:001673-001700
3D Integration is becoming a reality in device manufacturing. The TSV Middle process is becoming the dominant integration scenario. For this process flow the silicon wafer needs to be thinned to reveal the Cu TSV. Grinding is used to remove the bulk
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5642d9b6b47c5b0f70bc14dec71d4c6
https://doi.org/10.4071/2012dpc-wp11
https://doi.org/10.4071/2012dpc-wp11
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2011:001596-001620
3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::610e5796a2646a5ab82a29cabd0e1a4c
https://doi.org/10.4071/2011dpc-wp14
https://doi.org/10.4071/2011dpc-wp14
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2010:001030-001053
Thin wafers have become a basic need for a wide variety of new microelectronic products. Thinner die are being required to fit into thinner packages. Wafers that have been thinned using a final wet etch process on the backside have less stress compar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96fb0c0ac82b95097b5109b2af9b644a
https://doi.org/10.4071/2010dpc-tp33
https://doi.org/10.4071/2010dpc-tp33
Publikováno v:
2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
2.5D and 3D packaging continues to be a popular topic within the semiconductor industry. Several announcements have shown signs of adoption for the new packaging technology, especially for stacked DRAMi. The reveal of the Through Silicon Via (TSV) is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fba33dd3980bd09ecea48f785d552a8c
https://doi.org/10.1109/impact.2015.7365257
https://doi.org/10.1109/impact.2015.7365257
Autor:
Craig Allen, Laura Mauer, Kevin McLaughlin, Sian Collins, Ramey Youssef, John Taddei, Yongqiang Lu
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
This paper presents a wet process as a simple and cost-effective alternative to the polish/plasma etch TSV reveal process. By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49111c91d0743557fb322426ba44a7a9
https://doi.org/10.1109/ectc.2014.6897390
https://doi.org/10.1109/ectc.2014.6897390