Zobrazeno 1 - 7
of 7
pro vyhledávání: '"John R. Alvis"'
Autor:
M. Moosa, Philip J. Tobin, G.C.-F. Yeap, Andreas Hegedus, John R. Alvis, T.C. Chua, G. Miner, P. Abramowitz, Yongjoo Jeon, T. Y. Luo, N. Cave, L. Hebert, J.J. Lee, Hsing-Huang Tseng, S.G.H. Anderson, A. Sultan, J. Jeon, J. Jiang
Publikováno v:
IEEE Electron Device Letters. 23:704-706
Balancing gate leakage reduction, device performance, and gate dielectric reliability is a major challenge for oxynitride used as a gate dielectric for advanced technology. As compared to RTONO oxynitride, pMOSFET threshold voltage shift and transcon
Autor:
D. Dyer, D. Wristers, P. Ingersoll, Karl Wimmer, R. Stout, John R. Alvis, Yongjoo Jeon, P. Grudowski, J. Conner, D. Bonser, P. Abramowitz, T.V. Gompel, J. Pellerin, J.J. Lee, A. Duvallet, M. Foisy, K. Hellig, S. Lim, D. Hall, L. Vishnubhotla, S. Parihar, A. Nghiem, G.C.-F. Yeap, Kyle Patterson, W. Qi, M. Rendon, Yang Du, Y. Shiho, J. Chen, S. Jallepalli, Marilyn Irene Wright, K. Weidemann, M. Woo, David Burnett, T. Luo, Craig S. Lage, R. Singh, C. Reddy, M. Hall, H.-H. Tseng, S. Veeraraghavan, N. Benavides, N. Ramani
Publikováno v:
Scopus-Elsevier
We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction)
Autor:
K. C. Yu, M. Friedemann, T. Sparks, J. Reiss, T. Lii, R. Chowdhury, Paul R. Besser, V. Sheth, K. Junker, M. Olivares, D. Wristers, N. Ramani, Matthew A. Thompson, M. Schaller, S. Gonzales, Douglas J. Bonser, M. Celik, S. Crown, Y. Solomentsev, S. Shah, M. Moosa, D. Wu, S. Ufmani, T. Stephens, R. Islam, S. Park, Rick Carter, C. Goldberg, Bradley P. Smith, John L. Sturtevant, John R. Alvis, J. Chang, K. Strozewski, S.-C. Song, A.H. Perera, J. Fretwell, S. Kim, Akif Sultan, N. Cave, S. Chheda, C. Thomas, D. Eades, N. Benavides, B. Ho, D. Denning, S. Venkatesan, Cindy Reidsema Simpson, Brett Caroline Baker, Venkat Kolagunta, Kent G. Green, B. Melnick, Robert Fox, M. Sureddin
Publikováno v:
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
A modular 0.13 /spl mu/m CMOS platform has been developed to support a wide range of applications, including embedded non-volatile memory (NVM). The high performance core device with a 18 /spl Aring/ gate oxide supports the high end needs of the tech
Autor:
Nigel Cave, Carla M. Nelson-Thomas, John L. Sturtevant, Nancy Benavides, John R. Alvis, Douglas J. Bonser, Kyle Patterson, Karen L. Turnquest, William D. Taylor
Publikováno v:
SPIE Proceedings.
Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus L
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography X.
A patterned wafer inspection system using optical pattern filtering (OPF) has been integrated into sub-half micron semiconductor device pilot production lines (125 mm and 200 mm) for the purpose of process defect control. The optical pattern filterin
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Conference
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