Zobrazeno 1 - 3
of 3
pro vyhledávání: '"John Iacoponi"'
Autor:
Philip J. Oldiges, Hemanth Jagannathan, Kangguo Cheng, Christopher Prindle, C.-C. Yeh, R. Divakaruni, S. Kanakasabaphthy, Derrick Liu, Sean D. Burns, P. Montanini, T. Gow, Huiming Bu, Abhijeet Paul, Terry A. Spooner, Richard G. Southwick, Jin Cho, M. Celik, Mukesh Khare, Donald F. Canaperi, Young-Kwan Park, H. Mallela, Ravikumar Ramachandran, Bomsoo Kim, Dinesh Gupta, Balasubramanian S. Pranatharthi Haran, R. Kambhampati, M. Weybright, W. Yang, Vamsi Paruchuri, Tae-Chan Kim, R. Sampson, K. Kim, D. Chanemougame, John Iacoponi, Jay W. Strane, Ruilong Xie, D.I. Bae, Injo Ok, Matthew E. Colburn, T. Hook, Kang-ill Seo, Lars W. Liebmann, V. Sardesai, Hoon Kim, Neeraj Tripathi, H. Shang, M. Mottura, Reinaldo A. Vega, B. Hamieh, D. McHerron, Theodorus E. Standaert, Ju-Hwan Jung, S. Nam, E. Alptekin, Soon-Cheon Seo, Dechao Guo, J. G. Hong, Gen Tsutsui, Andreas Scholze, J. Jenq, Xiao Sun, Walter Kleemeier, James H. Stathis, Geum-Jong Bae
Publikováno v:
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fdd9e37b1ad7ef1b69d8d55e103e9fa
https://doi.org/10.1109/icsict.2014.7021207
https://doi.org/10.1109/icsict.2014.7021207
Autor:
Jeffrey C. Shearer, Philip J. Oldiges, Soon-Cheon Seo, Terry A. Spooner, Matthew E. Colburn, Ravikumar Ramachandran, V. Sardesai, Kang-ill Seo, Dinesh Gupta, Richard G. Southwick, Xiao Sun, S. Stieg, H. Cai, S. Kanakasabaphthy, Vamsi Paruchuri, R. Sampson, Lars W. Liebmann, Walter Kleemeier, Kisik Choi, Deok-Hyung Lee, Christopher Prindle, R. Divakaruni, H. Shang, Abhijeet Paul, T. Gow, D. McHerron, Dechao Guo, Fee Li Lie, J. Nam, Neeraj Tripathi, Ruilong Xie, R. Kambhampati, Muthumanickam Sankarapandian, Balasubramanian S. Pranatharthi Haran, Carol Boye, James H. Stathis, B. Hamieh, John Iacoponi, Christopher J. Waskiewicz, Geum-Jong Bae, Derrick Liu, Sanjay Mehta, Reinaldo A. Vega, Terence B. Hook, Min Gyu Sung, Jay W. Strane, D.I. Bae, Robin Chao, Hoon Kim, F. Nelson, Theodorus E. Standaert, L. Jang, Erin Mclellan, M. Celik, S. Nam, Tae-Chan Kim, C.-C. Yeh, Sean D. Burns, P. Montanini, Charan V. V. S. Surisetty, Raghavasimhan Sreenivasan, Ju-Hwan Jung, B. Lherron, S.-B. Ko, E. Alptekin, Huiming Bu, Injo Ok, Jin Cho, Mukesh Khare, J. G. Hong, Gen Tsutsui, Andreas Scholze, Bomsoo Kim, D. Chanemougame, M. Mottura, M. Weybright, H. Mallela, K. Kim, Hemanth Jagannathan, Chanro Park, J. Jenq, Donald F. Canaperi, Young-Kwan Park, R. Jung, Kangguo Cheng
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4d82166b734af3db83f196d83853ba5
https://doi.org/10.1109/vlsit.2014.6894342
https://doi.org/10.1109/vlsit.2014.6894342
Conference
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