Zobrazeno 1 - 1
of 1
pro vyhledávání: '"John Haeseon Lee"'
Publikováno v:
CICC
An all-digital measurement circuit, built in 45-nm SOI-CMOS, enables on-chip characterization of phase-locked loop (PLL) response to a self-induced phase step. This technique allows estimation of PLL closed-loop bandwidth and jitter peaking. The circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2453c60bcaf9fcaa30c240d601ada06
https://doi.org/10.1109/cicc.2009.5280739
https://doi.org/10.1109/cicc.2009.5280739
