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CICC
An all-digital measurement circuit, built in 45-nm SOI-CMOS, enables on-chip characterization of phase-locked loop (PLL) response to a self-induced phase step. This technique allows estimation of PLL closed-loop bandwidth and jitter peaking. The circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2453c60bcaf9fcaa30c240d601ada06
https://doi.org/10.1109/cicc.2009.5280739
https://doi.org/10.1109/cicc.2009.5280739
Autor:
Lee, John Haeseon
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and
Externí odkaz:
http://hdl.handle.net/1721.1/105948
Autor:
Lee, John Haeseon
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 93-96).
There has been much interest in dev
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 93-96).
There has been much interest in dev
Externí odkaz:
http://hdl.handle.net/1721.1/66034