Zobrazeno 1 - 10 of 54 pro vyhledávání: '"John E. Turner"'
1
A next generation architecture optimized for high density system level integration
Autor: C. McClintock, John E. Turner, A. Lee, David Jefferson, Richard G. Cliff, R. Altaf, Bruce B. Pedersen, J. Schleicher, K. Zaveri, M. Mejia, Christopher F. Lane, Srinivas T. Reddy, Frank Heile, N. Ngo
Publikováno v: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
Altera has developed a next generation architecture called APEX/sup TM/ to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a92843d453fd62b304ade8238c9b699e
https://doi.org/10.1109/cicc.1999.777268
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2
A 10 ns, 4000 gate, 160 pin CMOS EPLD developed on a 0.8 μm process
Autor: John C. Costello, Rakesh H. Patel, Dirk A. Reese, Myrong Wong, John E. Turner
Publikováno v: Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
The 160-pin EPM7192, an erasable programmable logic device (EPLD) with a system operating frequency in excess of 100 MHz, is described. This 192 macrocell device is the fastest EPLD at this logic density. The input to output propagation delay for thi
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::812d0faaee1d27de3018f3702cc8af5f
https://doi.org/10.1109/cicc.1993.590580
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3
A high density embedded array programmable logic architecture
Autor: William Leong, C.K. Sung, Richard G. Cliff, David Jefferson, C. McClintock, Srinivas T. Reddy, Wanli Chang, John E. Turner, Joseph Huang, T. Cope, Christopher F. Lane, Bahram Ahanin, Bonnie I. Wang
Publikováno v: Proceedings of Custom Integrated Circuits Conference.
An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c397aa85f3f394130190e784574ff10f
https://doi.org/10.1109/cicc.1996.510553
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4
A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability
Autor: S. Sekariapuram, Dirk A. Reese, M. Chu, Bezhad Nouban, R. Smolen, John E. Turner, G. Liang, E. Chun, Nghia Van Tran, Brad Vest, Minchang Liang, S. Cheung, John C. Costello, E. Lau, Myron W. Wong
Publikováno v: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
The methods and circuits used in the design of a high density, high performance, power efficient, complex PLD are discussed. The EPM9560A is the first member of the third generation MAX 9000 family. Developed on a 0.5 /spl mu/m triple layer metal pro
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::966835af7479fe568aa17c573db28449
https://doi.org/10.1109/cicc.1998.694977
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5
A silicon efficient FLEX 6000 programmable logic architecture
Autor: Khai Nguyen, John E. Turner, Kerry Veenstra, Richard G. Cliff, Joseph Huang, Chiakang Sung, Bonnie I. Wang, Xiaobao Wang, Bruce B. Pedersen
Publikováno v: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
An SRAM based PLD architecture ranging from 5000 to 24000 gates has been developed. The primary focus of the architecture is on low cost, high performance, and routability. Breakthroughs in interconnect scheme have been made to achieve flexible routi
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::22c947e35693d4dc288e60b05a325c6c
https://doi.org/10.1109/cicc.1998.694979
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6
A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability
Autor: V. Bocchino, M. Chu, John E. Turner, Myron W. Wong, Rakesh H. Patel, Dirk A. Reese, John C. Costello
Publikováno v: Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
This paper discusses a complex programmable logic device which provides up to 12,000 usable gates. The EPM9560 is the first member of the third-generation MAX 9000 family. It blends a multi-dimensional interconnect scheme, logic array block approach
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1b9a927e2711d9576a8a5d3cf81dc4aa
https://doi.org/10.1109/cicc.1995.518234
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7
Migration of a dual granularity globally interconnected PLD architecture to a 0.5μ TLM process
Autor: James A. Watson, Ninh D. Ngo, John E. Turner, Richard G. Cliff, K. Nguyen, Cameron McClintock, Chiakang Sung, Bonnie I. Wang, William Leong
Publikováno v: Field-Programmable Logic and Applications ISBN: 9783540602941
FPL
A global interconnect architecture with dual granularity demonstrates considerable migration capability from the original product on 0.8Μ two layer metal process by reducing die size to one third while nearly doubling system frequency when transferr
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2b6f86962c4fb0107dd1572166bf4883
https://doi.org/10.1007/3-540-60294-1_94
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9
Etch Selectivity Between Phosphorus‐Doped SiO2 and TiSi2
Autor: Konrad K. Young, Paul E. Riley, John E. Turner
Publikováno v: Journal of The Electrochemical Society. 140:L12-L13
The etch rates of phosphorus-doped SiO 2 (PSG) and TiSi 2 , which is used on source/drain, and polycrystalline silicon contacts of metal oxide semiconductor devices have been measured in an O 2 /CHF 3 plasma for a process designed to produce contact
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::44bffa601cd8d749b4adc6e4b5118a91
https://doi.org/10.1149/1.2056118
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