Zobrazeno 1 - 10 of 23 pro vyhledávání: '"John E. Barth"'
1
Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology
Autor: John E. Barth, Norman Robson, Troy L. Graves-Abe, Bishan He, Gary W. Maier, Douglas Charles Latulipe, Chandrasekharan Kothandaraman, Ben Himmel, Kevin R. Winstel, Tuan Vo, Spyridon Skordas, Deepika Priyadarshini, John W. Golz, Kristian Cauffman, Pooja R. Batra, Deepal Wehella Gamage, B. Peethala, Alex Hubbard, Wei Lin, Subramanian S. Iyer, Toshiaki Kirihata
Publikováno v: Journal of Low Power Electronics and Applications
Volume 4
Issue 2
Pages 77-89
Journal of Low Power Electronics and Applications, Vol 4, Iss 2, Pp 77-89 (2014)
For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling.
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::782026d416ddd879ee76075210c72f77
https://doi.org/10.3390/jlpea4020077
Zobrazit plný text záznamu
2
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
Autor: William Robert Reohr, R. Freese, John W. Golz, Jente B. Kuang, Paul C. Parries, Gregory J. Fredeman, Jethro C. Law, Trong V. Luong, Pamela Wilcox, Hien Minh Le, Abraham Mathews, David Dick, Hillery C. Hunter, Erik A. Nelson, Subramanian S. Iyer, Toshiaki Kirihata, Gary Koch, A. Khargonekar, Hung C. Ngo, John E. Barth, Peter Juergen Klim
Publikováno v: IEEE Journal of Solid-State Circuits. 44:1216-1226
We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f68712ec5bfaf69d78fe5b66dec9430d
https://doi.org/10.1109/jssc.2009.2014207
Zobrazit plný text záznamu
3
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
Autor: C. Tanner, K. Yanagisawa, Richard E. Matick, J. Griesemer, Hillery C. Hunter, Babar A. Khan, Paul C. Parries, Kim Hoki, John W. Golz, Subramanian S. Iyer, Gregory J. Fredeman, J. Harig, John E. Barth, R.P. Havreluk, T. Kirihata, Stanley E. Schuster, William Robert Reohr
Publikováno v: IEEE Journal of Solid-State Circuits. 43:86-95
As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro w
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3dc46e0324a6411f1637ffbc2350b8b3
https://doi.org/10.1109/jssc.2007.908006
Zobrazit plný text záznamu
4
Embedded DRAM: Technology platform for the Blue Gene/L chip
Autor: Paul C. Parries, John E. Barth, James P. Norum, L. R. Logan, S.S. Iyer, J. P. Rice, D. Hoyniak
Publikováno v: IBM Journal of Research and Development. 49:333-350
The Blue Gene®/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM u
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bd0575cd4a4bf0f7a09154d2c6b15c03
https://doi.org/10.1147/rd.492.0333
Zobrazit plný text záznamu
5
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining
Autor: Darren L. Anand, S. Sliva, Jeffrey H. Dreibelbis, Dale E. Pontius, Michael R. Nelms, Erik A. Nelson, S. Burns, Kevin W. Gorman, Adrian J. Paparelli, John E. Barth, G. Pomichter, John A. Fifield
Publikováno v: IEEE Journal of Solid-State Circuits. 40:213-222
This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improv
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::01a70e212ab54fca80057305bcaab0c8
https://doi.org/10.1109/jssc.2004.838001
Zobrazit plný text záznamu
6
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface
Autor: Jim Covino, S. Lamphier, P. Corson, R. Houghton, S. Burns, Harold Pilo, Darren L. Anand, John E. Barth
Publikováno v: IEEE Journal of Solid-State Circuits. 38:1974-1980
This paper describes a 144-Mb DRAM that operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121-mm/sup 2/ die is fabricated in a 0.13-/spl mu/m logic-based process with embedded DRAM. The cycle time is ach
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::07a3fc50c66c224c8452d3b9f4c3e02c
https://doi.org/10.1109/jssc.2003.818141
Zobrazit plný text záznamu
7
Processor-based built-in self-test for embedded DRAM
Autor: Howard Leo Kalter, Rex Ngo Kho, Jeffrey H. Dreibelbis, John E. Barth
Publikováno v: IEEE Journal of Solid-State Circuits. 33:1731-1740
A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256/spl times/16/spl times/128 to 2 K/spl times/16/spl times/256 (Word/spl times
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0d750df7304f0b49738906d016865447
https://doi.org/10.1109/4.726568
Zobrazit plný text záznamu
8
Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology
Autor: Kevin R. Winstel, Ben Himmel, Deepika Priyadarshini, Tuan Vo, Kristian Cauffman, Alex Hubbard, B. Peethala, Pooja R. Batra, Wei Lin, John W. Golz, Norman Robson, Gary W. Maier, Chandrasekharan Kothandaraman, Douglas Charles Latulipe, Bishan He, Spyridon Skordas, Deepal Wehella Gamage, Troy L. Graves-Abe, John E. Barth, Subramanian S. Iyer, Toshiaki Kirihata
Publikováno v: 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1fa750d399aadb8ae0d9c826c580c8ae
https://doi.org/10.1109/s3s.2013.6716515
Zobrazit plný text záznamu
10
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
Autor: Rajiv V. Joshi, Don Plass, Todd Weaver, John E. Barth, Steve Burns, Adis Vehabovic, Rouwaida Kanj
Publikováno v: VLSIC
The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read ‘1’ Isolation scheme, allowing a lower stored ‘1’ level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activ
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::336063a6f2e06db909f499c6a15cacc9
https://doi.org/10.1109/vlsic.2012.6243814
Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání

Omezení vyhledávání
Plný text Recenzováno Digitální knihovna AV ČR
Zdroje