Zobrazeno 1 - 4
of 4
pro vyhledávání: '"John D. Hyde"'
Autor:
Michael H. Thomas, Ronald A. Oliver, Robert M. Glidden, Dennis Kiyoshi Hara, Scott A. Cooper, David D. Dressler, Todd E. Humes, Terry D. Hass, Vadim Gutnik, C. Bockorick, Omer Onen, Kurt E. Sundstrom, John D. Hyde, C. Hagen, Alberto Pesavento, Christopher J. Diorio
Publikováno v:
IEEE Communications Magazine. 42:140-151
The availability of inexpensive CMOS technologies that perform well at microwave frequencies has created new opportunities for automated material handling within supply chain management (SCM) that in hindsight, be viewed as revolutionary. This articl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ea822a76f801fec3dfaa4bf99daf814
https://doi.org/10.1109/mcom.2004.1321406
https://doi.org/10.1109/mcom.2004.1321406
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:734-740
Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54e8402d4f81dad026bfe08fad31a609
https://doi.org/10.1109/jssc.2003.810049
https://doi.org/10.1109/jssc.2003.810049
Publikováno v:
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a 0.25 /spl mu/m CMOS logic process. We trim the static INL to /spl plusmn/0.3 LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm/sup
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c941743e4d43a27750b6c425cec3646
https://doi.org/10.1109/vlsic.2002.1015118
https://doi.org/10.1109/vlsic.2002.1015118
Autor:
Christopher J. Diorio, H. Notthoff, A. Oki, G. Chao, Todd E. Humes, M. Kintis, A. Lai, John D. Hyde
Publikováno v:
GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997.
We report a GaAs-AlGaAs fractional frequency-synthesizer IC with a 5.5 GHz feedback divider, 2 GHz reference divider, 500 MHz phase-frequency detector, 1 ns charge-pump pulses, gain-normalized output current, and 18 pA/sub rms///spl radic/Hz in-band
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d018ad8a427126a74948b8f40f17dbe
https://doi.org/10.1109/gaas.1997.628280
https://doi.org/10.1109/gaas.1997.628280