Zobrazeno 1 - 7
of 7
pro vyhledávání: '"John Badar"'
Publikováno v:
Microprocessors and Microsystems. 45:241-252
In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as "no cycle stealing"
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79e077d0a1cbc59a570687e8d6b71cfa
https://doi.org/10.1016/j.micpro.2016.05.012
https://doi.org/10.1016/j.micpro.2016.05.012
Autor:
Jose L. Neves, Ofer Geva, Anthony Saporito, Mark Cichanowski, Christopher J. Berry, Christian Jacobi, John Badar, Brian Bell, Christian Zoellin, L. Sigal, B. Huott, James D. Warnock, Richard F. Rizzolo, Jesse Surprise, S. Carey, Frank Malgioglio, Arthur J. O'Neill, Guenter Mayer, Robert J. Sonnelitter, John Isakson, Dina Hamid, Michael G. Wood, Ricardo H. Nigaglioni, David Wolpert, Dureseti Chidambarrao
Publikováno v:
ISSCC
The IBM Z microprocessor in the z14 system has been redesigned to improve performance, system capacity, and security [1] over the previous z13 system [2]. The system contains up to 24 central processor (CP) and 4 system controller (SC) chips. Each CP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3fc78d2a0a09b0b28c2104fc9ef5268
https://doi.org/10.1109/isscc.2018.8310171
https://doi.org/10.1109/isscc.2018.8310171
Autor:
Yuen Chan, Matthew M. Ziegler, Bronson Tim, Tobias Werner, Frank Malgioglio, Charudhattan Nagarajan, S. Carey, Michael A. Blake, Mark Cichanowski, Donald W. Plass, Brian W. Curran, D. Malone, Jeffrey A. Zitz, Pak-Kin Mak, Michael G. Wood, James D. Warnock, Yiu-Hing Chan, Gregory J. Fredeman, John Isakson, Friedrich Schroeder, Christopher J. Berry, John Badar, L. Sigal, Gerald Strevig, Guenter Mayer, Ruchir Puri, M. Mayo, Dieter Wendel, Gerard M. Salem, Daniel M. Dreps, Ricardo H. Nigaglioni
Publikováno v:
ISSCC
The next-generation System z design introduces a new microprocessor chip (CP) and a system controller chip (SC) aimed at providing a substantial boost to maximum system capacity and performance compared to the previous zEC12 design in 32nm [1,2]. As
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22145c646a2415fdbc0c5107fd1e305a
https://doi.org/10.1109/isscc.2015.7062930
https://doi.org/10.1109/isscc.2015.7062930
Autor:
Charudhattan Nagarajan, Sridhar H. Rangarajan, Y.H. Chan, John Badar, Y.-H. Chan, M. Mayo, S. Carey, Matt Ziegler, L. Sigal, Thomas Strach, Christopher J. Berry, Niels Fricke, Gerald Strevig, Jose L. Neves, Frank Malgioglio, Dieter Wendel, Donald W. Plass, Ruchir Puri, John Isakson, A. Aipperspach, D. Malone, Robert M. Averill, James D. Warnock, Gerard M. Salem, Friedrich Schroeder, K. Lind, Howard H. Smith, Michael H. Wood, Jesse Surprise, Ricardo H. Nigaglioni, Guenter Mayer, D. Phan
Publikováno v:
IBM Journal of Research and Development. 59:15:1-15:15
The two chips at the heart of the IBM z13™ system include a processor chip (referred to as the CP or Central Processor chip) and an L4 (Level 4) cache chip (referred to as the SC or System Controller chip), each 678 mm2 in area. The CP and SC chips
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09bb51eed69b2b63a4c613096a7a250d
https://doi.org/10.1147/jrd.2015.2446871
https://doi.org/10.1147/jrd.2015.2446871
Autor:
DOMKE, JENS, VATAI, EMIL, GEROFI, BALAZS, YUETSU KODAMA, WAHIB, MOHAMED, PODOBAS, ARTUR, MITTAL, SPARSH, PERICÀS, MIQUEL, LINGQI ZHANG, PENG CHEN, DROZD, ALEKSANDR, SATOSHI MATSUOKA
Publikováno v:
ACM Transactions on Architecture & Code Optimization; Dec2023, Vol. 20 Issue 4, p1-26, 26p
Autor:
SINGH, SARABJEET, SURANA, NEELAM, PRASAD, KAILASH, JAIN, PRANJALI, MEKIE, JOYCEE, AWASTHI, MANU
Publikováno v:
ACM Transactions on Architecture & Code Optimization; Jun2023, Vol. 20 Issue 2, p1-20, 20p
Autor:
Shah, Parth, Shenoy, Ranjal Gautham, Srinivasan, Vaidyanathan, Bose, Pradip, Buyuktosunoglu, Alper
Publikováno v:
ACM Transactions on Architecture & Code Optimization; Mar2023, Vol. 20 Issue 1, p1-26, 26p