Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Johan Janssens"'
Autor:
Johan Janssens, Weize Chen, Rick Jerome, Jaroslav Pjencak, Mark Griswold, Santosh Menon, Moshe Agam
Publikováno v:
2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
A cost effective method to extend a 70V bulk BCD technology to a 200V SOI BCD technology is presented. The new approach replaces the floating n-type buried layer (NBL) in the bulk technology with the buried oxide (BOX) in silicon-on-insulator (SOI).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dadb415eed05b6a0406035ea438367fc
https://doi.org/10.23919/ispsd50666.2021.9452294
https://doi.org/10.23919/ispsd50666.2021.9452294
Publikováno v:
2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
The isolation capabilities of the Floating N-type Buried Layer (NBL) architecture are discussed and explained in reference to connected NBL. The non-deterministic NBL potential requires new considerations for lateral and vertical parasitics. These pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e53ec30d51b9bd5bd55cab5b2f86198
https://doi.org/10.23919/ispsd50666.2021.9452202
https://doi.org/10.23919/ispsd50666.2021.9452202
Physical and Electrical Characterization of Deep Trench Isolation in Bulk Silicon and SOI Substrates
Autor:
Sallie Hose, Lahcen Boukhanfra, Lan Su, Masaichi Eda, Rick Jerome, Weize Chen, Jaroslav Pjencak, Thomas F. Long, Johan Janssens, Moshe Agam, Kenn Bates
Publikováno v:
2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
In this paper the authors present case studies for physical and electrical characterization of Deep Trench Isolation (DTI) in bulk silicon and SOI substrates. For bulk silicon, experimental results demonstrate how the effectiveness of the isolation i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee709b0dc0ae9329ba2354d27b3c85ae
https://doi.org/10.1109/asmc51741.2021.9435655
https://doi.org/10.1109/asmc51741.2021.9435655
Publikováno v:
2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
In a given multipurpose BCD technology, the device implants are set by the main workhorse devices. Typically, doping levels are determined by optimizing Rsp and other key properties of the main devices, often settling with optimized Rsp-Bvdss trade-o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::817e51b1ce429e0d0c238624bba16fce
https://doi.org/10.1109/ispsd46842.2020.9170036
https://doi.org/10.1109/ispsd46842.2020.9170036
Autor:
Johan Janssens
Publikováno v:
2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
The floating buried layer isolation architecture enables a cost reduction of high-voltage Bulk BCD technologies, while providing circuit designers with a footprint and degrees of freedom similar to SOI, without its disadvantages. The concept embraces
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7d3ca371c3eb1f01420109dbc0974be
https://doi.org/10.1109/ispsd46842.2020.9170056
https://doi.org/10.1109/ispsd46842.2020.9170056
Publikováno v:
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
A low-power, broadband LNA has been integrated in a standard 0.5 /spl mu/m CMOS process. The presented CMOS LNA offers a noise figure better than 3.3 dB up to 970 MHz while drawing only 3.4 mA from a 3.0 V supply. The circuit employs a topology witho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36cae2b9ed4476fb97045f622155e8f3
https://doi.org/10.1109/cicc.1998.694910
https://doi.org/10.1109/cicc.1998.694910
Publikováno v:
Analog Circuit Design ISBN: 9781461286288
Since several years research has been carried out on the design of RF circuits in CMOS technologies. Since then, the usability of CMOS for RF design has been demonstrated by several research groups. However, there are still some fundamental problems
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0547172be883963a8b645821ba461ef
https://doi.org/10.1007/978-1-4613-1443-1_4
https://doi.org/10.1007/978-1-4613-1443-1_4
Autor:
Michiel Steyaert, Johan Janssens
Publikováno v:
Analog Circuit Design ISBN: 9781441950710
In general it is believed that the implementation of low-noise RF amplifiers in CMOS at a power dissipation competitive with bipolar technologies requires the use of narrow-band techniques. In this paper the design of power-efficient broadband low-no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fe2a982af00ef913e26564aaa8d65cc
https://doi.org/10.1007/978-1-4757-2983-2_14
https://doi.org/10.1007/978-1-4757-2983-2_14
Autor:
Michel Steyaert, Johan Janssens
Publikováno v:
Electronics Letters. 35:672
Low-noise and power amplifiers commonly use inductive degeneration to match the inherently capacitive MOS device to the source impedance R/sub S/. It is shown how this matching technique can be refined by incorporating the non-quasistatic effect and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d6317778d2ec38664894bfd4d332058
https://doi.org/10.1049/el:19990432
https://doi.org/10.1049/el:19990432
Autor:
Johan Janssens, H. Steyaert
Publikováno v:
Electronics Letters. 35:1278
MOS noise performance under source matching constraints is analysed for an improved impedance matching scheme, using both classical and non-quasistatic noise models. The tradeoff between achieving a low noise figure and a high power gain when preserv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87168a5ff9ff6f1fd246f63cd2bd54a3
https://doi.org/10.1049/el:19990837
https://doi.org/10.1049/el:19990837