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pro vyhledávání: '"Joey Yurgelon"'
Publikováno v:
MWSCAS
An FPGA based 2nd-order passive KD1S sigma-delta modulator was designed, simulated and tested. The design is implemented on an Altera Cyclone IV EP4CE115 FPGA. All active components such as digital logic, clock circuitry, and registers are located in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ace89ac9d2bee7f0dbd8abe7d789f442
https://doi.org/10.1109/mwscas.2015.7282136
https://doi.org/10.1109/mwscas.2015.7282136
