Zobrazeno 1 - 10 of 15 pro vyhledávání: '"Joerg Winkler"'
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Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development
Autor: Zhigang Song, Tarl Gordon, Teng-Yin Lin, Kan Zhang, Neerja Bawaskar, Steve Crown, Yandong Liu, Martin O'tool, Kannan Sekar, Toni Laaksonen, Daniel Greenslit, Mark Lagus, Ishtiaq Ahsan, Bill Evans, Joerg Winkler, Shahrukh Khan, DK Sohn, Frank Barth, John Masnik
Publikováno v: 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL proc
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::af9c6803b34a79dc6e26839fa55284f7
https://doi.org/10.1109/asmc.2019.8791769
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7
Low Cost and Highly Manufacturable MOL/BEOL Constructs in 22FDSOI Technology for High Performance and Low Power Applications
Autor: Mahbub Rashed, Joerg Winkler, Frank Barth, Ram Prasad Gopannagari, Shibly S. Ahmed, Navneet Jain, Atul Kumar Kashyap, Thomas Herrmann, Siddiqi Arif A, James Blatchford, Sushama Davar, Anurag Mittal, Juhan Kim, Jeff Kim, Jens Pika, Michael Zier, Sravan Kumar Tekuru, Siva Krisha Potta, Jamie Schaeffer, Sunil Machha
Publikováno v: 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM).
A highly optimized 22FDSOI Logic Architecture for Power, Performance, Area (PPA) and cost is presented in this paper. Unique features of FDSOI technology including channel strain based PFET transistor performance enhancement are further advanced with
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fb9845920a422f37bb924cfa85797f6a
https://doi.org/10.1109/edtm.2018.8421481
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