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pro vyhledávání: '"Joel M. Tendler"'
Publikováno v:
IBM Journal of Research and Development. 49:505-521
This paper describes the implementation of the IBM POWER5TM chip, a two-way simultaneous multithreaded dual-core chip, and systems based on it. With a key goal of maintaining both binary and structural compatibility with POWER4TM systems, the POWER5
Publikováno v:
IEEE Micro. 24:40-47
IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chip
Autor:
Victor Zyuban, Alper Buyuktosunoglu, Balaram Sinharoy, John Barry Griswell, Zhigang Hu, Hans M. Jacobson, Joel M. Tendler, D. Logan, Pradip Bose, Lee Evan Eisen, Richard J. Eickemeyer
Publikováno v:
HPCA
Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future proce
Autor:
Joel M. Tendler
Publikováno v:
IBM Journal of Research and Development. 49:503-504
Publikováno v:
ACM Transactions on Mathematical Software. 4:339-368
Publikováno v:
ACM Transactions on Mathematical Software. 4:399-403