Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Joachim Gerhard Clabes"'
Autor:
Joachim Gerhard Clabes, Joshua Friedrich, J. Kahle, William J. Starke, Daniel M. Dreps, Victor Zyuban, James D. Warnock, Robert Alan Cargnoni, S. Weitzel, Scott A. Taylor, Phillip G. Williams, Jose Angel Paredes, Dieter Wendel, J. Pille, Gaurav Mittal, Saiful Islam, G Smith, J. A. Van Norstrand, Balaram Sinharoy, Phillip J. Restle, David A. Hrusecky, Sam Gat-Shang Chu, Ronald Nick Kalla, Jentje Leenstra
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:145-161
This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 56
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9efa8df1eb9cc07c1be4577681cd9147
https://doi.org/10.1109/jssc.2010.2080611
https://doi.org/10.1109/jssc.2010.2080611
Autor:
J. Keaty, Joachim Gerhard Clabes, C. J. Kircher, Phillip J. Restle, John George Petrovick, James D. Warnock, Carl J. Anderson, B. A. Zoric, Byron L. Krauter
Publikováno v:
IBM Journal of Research and Development. 46:27-51
The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a024e2dbfee5ce608b1811134c6844a8
https://doi.org/10.1147/rd.461.0027
https://doi.org/10.1147/rd.461.0027
Autor:
T.M. Skergan, Phillip J. Restle, N. Schwartz, Joachim Gerhard Clabes, R.L. Franch, Norman Karl James, S.C. Wilson, William V. Huott
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
On-chip timing measurement (Skitter) circuits are included on the Power5 microprocessor. By cross-coupling the 3 Skitter instances, the combined effect of jitter, skew, and supply noise can be measured for all cycles of a pattern or an application. S
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5878ecc92456f9ab22d12fd6cfe0e14
https://doi.org/10.1109/isscc.2004.1332740
https://doi.org/10.1109/isscc.2004.1332740
Autor:
J. Dawson, Mike Lee, S. Dodson, Phillip J. Restle, Balaram Sinharoy, G. Gorman, N. Schwartz, Steve Runyon, Ronald Nick Kalla, Joachim Gerhard Clabes, M. Goulet, Jack DiLullo, J. Wagoner, Mark D. Sweet, L. Powell, Paul H. Muench, J. McGill, Donald W. Plass, Michael Stephen Floyd, Joshua Friedrich, Sam Gat-Shang Chu
Publikováno v:
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d86faeb3de9bea64e836b981ea22aa56
https://doi.org/10.1109/icicdt.2004.1309931
https://doi.org/10.1109/icicdt.2004.1309931
Autor:
Joachim Gerhard Clabes, Michael Normand Goulet, Mark D. Sweet, Donald W. Plass, Balaram Sinharoy, Gary Alan Gorman, Ronald Nick Kalla, Steve Runyon, Larry Powell, Phillip J. Restle, Joseph McGill, Mike Lee, Paul H. Muench, James Donald Wagoner, James W. Dawson, Michael Stephen Floyd, Jack DiLullo, Steve Dodson, Nicole Schwartz, Joshua Friedrich, Sam Gat-Shang Chu
Publikováno v:
DAC
POWER5 offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support. The 276M transistor processor is implemented in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94b0caf8594f41be065ac17fa88f5928
https://doi.org/10.1145/996566.996749
https://doi.org/10.1145/996566.996749
Autor:
John George Petrovick, Jack DiLullo, Carl J. Anderson, J. Keaty, Joachim Gerhard Clabes, Shao-Fu S. Chu, P. E. Dudley, James D. Warnock, J. Wagoner, G. Nussbaum, S. Weitzel, B. A. Zoric, R. Weiss, G. Plum, Steve Runyon, Byron L. Krauter, Bradley McCredie, Pong-Fei Lu, S. Schmidt, Michael R. Scheuermann, Phillip J. Restle, Craig R. Carter, J. LeBlanc, J.M. Tendier, P. Harvey
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dad8d8143abf2e20d495527032da1d11
https://doi.org/10.1109/isscc.2001.912617
https://doi.org/10.1109/isscc.2001.912617
Autor:
Joachim Gerhard Clabes, B. D. Silverman, A. R. Rossi, D. C. Hofer, Pia Naoko Sanda, Paul S. Ho
Publikováno v:
Journal of Polymer Science Part A: Polymer Chemistry. 26:1199-1205
The results of XPS measurements and molecular orbital calculations performed on the fluorine containing polyimide, PMDA–BDAF, are presented. The calculated carbon 1s (C1s) core energy level positions are compared with the level positions inferred f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b99a571a829a36cb131219335dce9ba2
https://doi.org/10.1002/pola.1988.080260420
https://doi.org/10.1002/pola.1988.080260420