Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Jiunn-Yann Tsai"'
Publikováno v:
IEEE Transactions on Electron Devices. 45:1946-1952
Very shallow elevated n/sup +//p junctions formed by arsenic implant into or through cobalt silicide (CoSi/sub 2/) formed on selective epitaxial layers and their application to deep submicron n-channel MOSFETs were studied for the first time. PREDICT
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00359f3d952d006a341602550a10f34c
https://doi.org/10.1109/16.711360
https://doi.org/10.1109/16.711360
Autor:
P.P. Apte, Jiunn-Yann Tsai
Publikováno v:
Thin Solid Films. 270:589-595
A reliable TiSi 2 TiN stack thickness model is an essential component for modeling the titanium salicide process, and such a model is not well-developed in current process simulators and in the literature. To determine this model, a design of experim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20973912dca1278ebdebde49a7fdaee7
https://doi.org/10.1016/0040-6090(96)80081-2
https://doi.org/10.1016/0040-6090(96)80081-2
Publikováno v:
Journal of Applied Physics. 69:4354-4363
This work investigates the characteristics of PtSi‐silicided p+n shallow junctions fabricated by implanting BF+2 ions into either the Pt/Si (ITM scheme) or the PtSi/Si (ITS scheme) structure followed by annealing in N2 furnace at temperatures from
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05704e21224536e4b2ddd28cd275f295
https://doi.org/10.1063/1.348359
https://doi.org/10.1063/1.348359
Publikováno v:
Journal of Applied Physics. 67:3530-3533
High‐temperature stability of the F+‐ or BF+2 ‐implanted PtSi thin film was investigated. For the PtSi films that received F+ implantation, the film characteristics remain unchanged even after annealing at 800 °C for 90 min, while for those wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c9e1c5f21a7bf089fbdf855aa224187
https://doi.org/10.1063/1.345327
https://doi.org/10.1063/1.345327
Publikováno v:
IEEE Electron Device Letters. 19:348-350
The gate oxide thickness increase in PMOSFET devices with BF/sub 2/ implanted p/sup +/ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4642b35cc4b00105edbac4de425a19b9
https://doi.org/10.1109/55.709640
https://doi.org/10.1109/55.709640
Publikováno v:
IEEE Electron Device Letters. 17:331-333
The drain-induced-barrier-lowering (DIBL) considerations of the extended drain structure were studied using two-dimensional (2-D) device simulations in the tenth-micrometer regime. We found that the drain extension length must be kept at a minimum in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::465287fe5581a56202c78888e45d8da9
https://doi.org/10.1109/55.506358
https://doi.org/10.1109/55.506358
Publikováno v:
1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.
A Lightly-Doped-Drain (LDD) structure was optimized by extensive process and device simulations with advanced mobility and impact ionization models for sub-quarter-/spl mu/m devices. A quadratic response-surface-model (RSM) was derived from Design-of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9210d41011f9f7aa7d918c8842e20c40
https://doi.org/10.1109/vtsa.1995.524705
https://doi.org/10.1109/vtsa.1995.524705
Publikováno v:
SPIE Proceedings.
Nitride LDD spacer material presents itself as a viable option for oxide spacer because of two important reasons; 1) possibility of reducing in the contact-poly spacing 2) possibility of achieving higher drive current. (nitride spacer material has a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bbda5cf93bd02c973d67b48dc2158465
https://doi.org/10.1117/12.324387
https://doi.org/10.1117/12.324387
Publikováno v:
SPIE Proceedings.
As MOSFET feature sizes are scaled down to 0.1 micrometers and below, new techniques are required to develop and fabricate shallow, low contact resistance, and low leakage S/D junctions. In this study, 2D device simulations have been performed to com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdc86348d2e94c673b08d6d82a9f36f8
https://doi.org/10.1117/12.250863
https://doi.org/10.1117/12.250863
Publikováno v:
MRS Proceedings. 402
Two major concerns for silicidation of ultra-shallow junctions, namely the silicon-consumption- induced junction leakage and the series resistance increase, were compared among conventional post-junction-silicide (PJS) contact, silicide-as-a-diffusio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03523eaae8a04922757a27f69748df8d
https://doi.org/10.1557/proc-402-245
https://doi.org/10.1557/proc-402-245