Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Jiun-hsin Liao"'
Publikováno v:
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS).
Parallel test capability, enabled by numerous independent measurement channels has significantly increased throughput in parametric testing. It involves testing of numerous devices simultaneously synchronously or asynchronously. The number of devices
Publikováno v:
Proceedings of the 2015 International Conference on Microelectronic Test Structures.
This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the e
Publikováno v:
ECS Transactions. 3:1211-1222
Device performance and reliability are of concern for devices fabricated on strained Si wafers. For strained Si formed by SiGe crystal growth, defects are of particular interest. We characterized such SiGe samples by pulsed MOS capacitor, gate oxide
Publikováno v:
2012 IEEE International Conference on Microelectronic Test Structures.
We present a simple test structure to measure C-V and I-V curves of the same nominal size FET. The structure is simple enough to be used for technology development, requires only first metal for routing, and allows parallel test. It is an extension o
Publikováno v:
2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
In this paper we present an early detection mechanism for semiconductor circuit yield prediction and tracking. Several discrete devices used as components of functional circuits have been examined by their first-metal level test data and correlated t
Publikováno v:
2011 IEEE ICMTS International Conference on Microelectronic Test Structures.
We report on Front-End-Of-Line Quadrature-clocked Voltage-dependent Capacitance Measurement (QVCM), a charge based capacitance measurement technique applicable to modern logic CMOS technologies with leaky gate oxides. QVCM test structures are designe
Autor:
Louis V. Medina, John A. Williamson, Ronald C. Geiger, Ernesto Shiling, Jiun-Hsin Liao, R. P. Robertazzi, Garry Moore
Publikováno v:
ITC
Continuing scaling trends in semiconductor technology, as well as the test requirements of new technologies being incorporated with mainstream silicon integrated circuits, has increased the complexity of parametric and defect structure testing. New t
Characterization of Strained Si/SiGe With Pulsed MOS Capacitor and Gate Oxide Integrity Measurements
Autor:
Jiun-Hsin Liao, Dieter Schroder
Publikováno v:
ECS Meeting Abstracts. :1523-1523
not Available.
Publikováno v:
2011 IEEE International Conference on Microelectronic Test Structures (ICMTS); 2011, p4-7, 4p
Publikováno v:
Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI; 2011, p1-4, 4p